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Details, datasheet, quote on part number:HM-65262
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TM
HM-65262
16K x 1 Asynchronous CMOS Static RAM
Description
The HM-65262 is a CMOS 16384 x 1-bit Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle times and ease of use. The HM-65262 is available in both JEDEC standard 20 pin, 0.300 inch wide CERDIP and 20 pad CLCC packages, providing high boardlevel packing density. Gated inputs lower standby current, and also eliminate the need for pull-up or pull-down resistors. The HM-65262, a full CMOS RAM, utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles. This stability also improves the radiation tolerance of the RAM over that of four transistor (4T) devices.
March 1997
Features
· Fast Access Time . . . . . . . . . . . . . . . . . . . 70/85ns Max · Low Standby Current. . . . . . . . . . . . . . . . . . . . 50µA Max · Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max · Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20µA Max · TTL Compatible Inputs and Outputs · JEDEC Approved Pinout · No Clocks or Strobes Required · Temperature Range . . . . . . . . . . . . . . . +55oC to +125oC · Equal Cycle and Access Time · Single 5V Supply · Gated Inputs-No Pull-Up or Pull-Down Resistors Required
Ordering Information
P ACKAGE CE RDIP JAN # SMD# CLCC (SMD#) NOTE: 1. Access Time/Data Retention Supply Current. TEMP. RANGE -40oC to +85oC -55oC to +125oC -55oC to +125oC -55oC to +125oC 70ns/20µA (NOTE 1) 85ns/20µA (NOTE 1) HM1-65262B-9 29109BR A 8413203RA 8413203YA HM1-65262-9 29103BRA 8413201RA 8413201YA (NOTE 1) 85ns/400µA PKG. NO. F20.3 F20.3 F20.3 J20.C
Pinouts
HM-65262 (CERDIP) TOP VIEW HM-65262 (CLCC) TOP VIEW
VCC A13 A1 A0 A1 A2 A3 A4 A5 A6 Q W 1 2 3 4 5 6 7 8 9 20 VCC 19 A13 18 A12 17 A11 16 A10 15 A9 14 A8 13 A7 12 D 11 E A2 3 A3 4 A4 5 A5 6 A6 7 Q8 9 1 0 11 12 W GND E D 2 A0
1 2 0 19 18 A12 17 A11 16 A10 15 A9 14 A8 13 A7
A0 - A13 E Q D V SS/GND V CC W
Address Input Chip Enable/Power Down Data Out Data In Ground Power (+5) Write Enable
GND 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1
FN3002.2
HM-65262 Functional Diagram
A0 A1 A2 A3 A4 A12 A13
A 7 RO W RO W ADDRESS DECODER 128 MEMORY ARRAY 1 28 X 128 BUFFER A (1 OF 128) 7 128
D
COLUMN DECODER (1 OF 128) AND I / O CIRCUITRY A 7 A 7
Q
E
COLUMN ADDRESS BUFFERS
W
2
A7 A8 A9 A10 A11 A5 A6
HM-65262
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for all grades . . . . . -0.3V to VCC +0.3V Typical Derating Factor. . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
JC Thermal Resistance (Typical) JA CERDIP Package. . . . . . . . . . . . . . . . . . 66oC/W 13oC/W CLCC Package . . . . . . . . . . . . . . . . . . . 75oC/W 18oC/W Maximum Storage Temperature Range . . . . . . . . . . . . -65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-65262B-9, HM-65262-9, HM-65262C-9 . . . . .-40oC to +85oC
DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-65262B-9, HM-65262-9, HM-65262C-9)
LIMITS SYMBOL ICCS B1 PARAMETER S tandby Supply Current MIN - od ICCSB ICCEN ICCOP ICCDR S tandby Supply Current E nabled Supply Current Operating Supply Current (Note 1) Data Retention Supply Current ICCDR1 Data Retention Supply Current VCCDR II I OZ VIL V IH VOL VOH1 VOH2 Data Retention Supply Voltage Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Note 2) 2.0 -1.0 -1.0 -0.3 2.2 2.4 VCC -0.4 M AX 50 900 5 50 50 20 400 30 550 +1.0 +1.0 0.8 V CC +0.3 0.4 UNITS µA µA mA mA mA µA µA µA µA V µA µA V V V V V VI = VCC or GND, VCC = 5.5V VIO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 8.0mA, VCC = 4.5V IO = -4.0mA, VCC = 4.5V IO = -100µA, VCC = 4.5V TEST CONDITIONS HM-65262B-9, HM-65262-9, IO = 0mA, E = VCC -0.3V, V CC = 5.5V HM-65262C-9, IO = 0mA, E = VCC -0.3V, V CC = 5.5V E = 2.2V, IO = 0mA, VCC = 5.5V E = 0.8V, IO = 0mA, VCC = 5.5V E = 0.8V, IO = 0mA, f = 1MHz, VCC = 5.5V HM-65262B-9, HM-65262-9, VCC = 2.0V, E = VCC HM-65262C-9, VCC = 2.0V, E = VCC HM-65262B-9, HM-65262-9, VCC = 3.0V, E = VCC HM-65262C-9, VCC = 3.0V, E = VCC
Capacitance TA = +25oC
SYMBOL CI CIO NOTES : 1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. PARAMETER Input Capacitance (Note 2) Input/Output Capacitance (Note 2) M AX 10 12 UNITS pF pF TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
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