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Details, datasheet, quote on part number:HM-6518/883
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Datasheet text preview:
TM
HM-6518/883
1024 x 1 CMOS RAM
Description
The HM-6518/883 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6518/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
March 1997
Features
· This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max · Low Power Operation . . . . . . . . . . . . . .20mW/MHz Max · Fast Access Time . . . . . . . . . . . . . . . . . . . . . 180ns Max · Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min · TTL Compatible Input/Output · High Output Drive - 2 TTL Loads · High Noise Immunity · On-Chip Address Register · Two-Chip Selects for Easy Array Expansion · Three-State Output
Ordering Information
PACKAGE CERDIP TEMP. RANGE -55oC to +125oC PART NUMBER HM1-6518/883 PKG. NO. F18.3
Pinout
HM-6518/883 (CERDIP) TOP VIEW
S1 E A0 A1 A2 A3 A4 Q G ND 1 2 3 4 5 6 7 8 9 18 VCC 17 S2 16 D 15 W 14 A9 13 A8 12 A7 11 A6 10 A5
PIN A E W S D Q
D ESCRIPTION Address Input Chip Enable Write Enable Chip Select Data Input Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2986.1
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HM-6518/883 Functional Diagram
A5 A6 A7 A8 A9 A LATCHED ADDRESS REGISTER 5 A 5 G D 32 GATED COLUMN DECODER AND DATA I/O D Q A GATED ROW DECODER 32 32 x 32 MATRIX
A
LATCH L
Q
W A E
5 A
5
LATCHED ADDRESS REGISTER
S1, S2
A0 A1 A2 A3 A4
NOTES : 1. All lines positive logic - active high. 2. Three-state buffers: A high output active. 3. Data latches: L high Q = D; Q Latches on rising edge of L. 4. Addr ess latches and gated decoders: Latch on falling edge of E and gate on falling edge of E.
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HM-6518/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) CERD IP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC JA JC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . .VCC -2.0V to VCC Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1936 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. HM- 6518/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PA RAME TER Output Low Voltage Output High Voltage Input Leakage Current Output Leakage Current Data Retention Supply Current HM-6518B /883 HM-6518/883 Operating Supply Current ICCOP SYMBOL V OL VOH II IOZ ICCDR (NOTE 1) CONDITIONS V CC = 4.5V, IOL = 3.2mA VCC = 4.5V, IOH = -0.4mA V CC = 5.5V, VI = GND or VCC VCC = 5.5V, VO = GND or VCC V CC = 2.0V, E = VCC, IO = 0mA, VI = VCC or GND V CC = 5.5V, (Note 2), E = 1MHz, IO = 0mA, VI = VCC or GND V CC = 5.5V, IO = 0mA, VI = VCC or GND GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC 1, 2, 3 -55oC TA +125oC 5 10 4 µA µA mA MIN 2.4 -1.0 -1.0 M AX 0.4 +1.0 +1.0 UNITS V V µA µA
S tandby Supply Current
ICCSB
1, 2, 3
-55oC TA +125oC
-
10
µA
NOTES : 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP.
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