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Details, datasheet, quote on part number:HM-6518
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Datasheet text preview:
TM
HM-6518
1024 x 1 CMOS RAM
Description
The HM-6518 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6518 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed overtemperature.
M arch 1997
Features
· · · · · · · Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max Low Power Operation . . . . . . . . . . . . . .20mW/MHz Max Fast Access Time . . . . . . . . . . . . . . . . . . . . . 180ns Max Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min TTL Compatible Input/Output High Output Drive - 2 TTL Loads High Noise ImmunitTwo-Chip Selects for Easy Array Expansion · On-Chip Address Register · Three-State Output
Ordering Information
P ACKAGE CERDIP TEMP. RANGE 180ns 250ns HM16518-9 PKG. NO. F18.3 -40oC to +85oC HM16518B- 9
Pinout
HM-6518 (CERDIP) TOP VIEW
S1 E A0 A1 A2 A3 A4 Q GND 1 2 3 4 5 6 7 8 9 18 VCC 17 S2 16 D 15 W 14 A9 13 A8 12 A7 11 A6 10 A5
PIN PIN A E W S
DESCRIPTION DESCRIPTION Address Input Chip Enable Write Enable Chip Select
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2987.1
1
HM-6518 Functional Diagram
A5 A6 A7 A8 A9 A LATCHED ADDRESS REGISTER 5 A 5 G D 32 GATED COLUMN DECODER AND DATA I/O D Q A GATED ROW DECODER 32 32 x 32 MATRIX
A
LATCH L
Q
W A E
5 A
5
LATCHED ADDRESS REGISTER
S1, S2
A0 A1 A2 A3 A4
NOTES : 1. All lines positive logic - active high. 2. Three-state buffers: A high output active. 3. Data latches: L high Q = D; Q Latches on rising edge of L. 4. Addr ess latches and gated decoders: Latch on falling edge of E and gate on falling edge of E.
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HM-6518
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) CERD IP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC JA JC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6518B-9, HM-6518-9 . . . . . . . . . . . . . . . . . . . - 40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1936 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6518B-9, HM-6518-9)
LIMITS PARAMETER S tandby Supply Current Operating Supply Current (Note 1) Data Retention Supply Current HM-6518B -9 HM-6518-9 VCCDR II IOZ VIL VIH V OL VOH SYMBOL ICCSB ICCOP ICCDR MIN 2.0 -1.0 -1.0 -0.3 VCC -2.0 2.4 MAX 10 4 5 10 +1.0 +1.0 0.8 VCC +0.3 0.4 UNITS µA mA µA µA V µA µA V V V V VI = VCC or GND, VCC = 5.5V VO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 3.2mA, VCC = 4.5V IO = -0.4mA, VCC = 4.5V TEST CONDITIONS IO = 0mA, VI = VCC or GND, VCC = 5.5V E = 1MHz, IO = 0mA, VI = VCC or GND, VCC = 5.5V VCC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC
Data Retention Supply Voltage Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Capacitance TA = +25oC
PARAMETER Input Capacitance (Note 2) Output Capacitance (Note 2) NOTES: 1. Typical derating 1.5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. SYMBOL CI CO M AX 6 10 UNITS pF pF TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
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