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Details, datasheet, quote on part number:HM-6516/883
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Datasheet text preview:
TM
HM-6516/883
2K x 8 CMOS RAM
Description
The HM-6516/883 is a CMOS 2048 x 8 Static Random Access Memory. Extremely low power operation is achieved by the use of complementary MOS design techniques. This low power is further enhanced by the use of synchronous circuit techniques that keep the active (operating) power low, which also gives fast access times. The pinout of the HM6516/883 is the popular 24 pin, 8-bit wide JEDEC Standard which allows easy memory board layouts, flexible enough to accommodate a variety of PROMs, RAMS, EPROMs, and ROMs . The HM-6516/883 is ideally suited for use in microprocessor based systems. The byte wide organization simplifies the memory array design, and keeps operating power down to a minim um because only one device is enabled at a time. The address latches allow very simple interfacing to recent generation microprocessors which employ a multiplexed address/data bus. The convenient output enable control also simplifies multiplexed bus interfacing by allowing the data outputs to be controlled independent of the chip enable.
March 1997
Features
· This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · Low Power Standby. . . . . . . . . . . . . . . . . . . 275µW Max · Low Power Operation . . . . . . . . . . . . . .55mW/MHz Max · Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max · Industry Standard Pinout · Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC · TTL Compatible · Static Memory Cells · High Output Drive · On-Chip Address Latches · Easy Microprocessor Interfacing
Ordering Information
120ns HM1-6516B/883 HM4-6516B/883 200ns HM1-6516/883 TEMPERATURE RANGE PACKAGE -55oC to 125oC -55oC to +125oC CERDIP CL CC PKG. NO. F24.6 J32.A
Pinouts
HM-6516/883 (CERDIP ) TOP VIEW
NC A7
HM-6516/883 ( CLCC) TOP VIEW
VCC NC NC NC NC
PIN NC
29 A8 28 A9 27 NC 26 W 25 G 24 A1 0 23 E 22 DQ7 21 DQ6
DESCR IPTION No Connect Address Inputs Chip Enable/Power Down Ground
A7 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 DQ0 9 DQ1 10 DQ2 11 GND 12
24 VCC 23 A8 22 A9 21 W 20 G 19 A10 18 E 17 DQ7 16 DQ6 15 DQ5 14 DQ4 13 DQ3
4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 1 1 NC 12 DQ 0 1 3
3
2
1
32 31 30
A0 - A10 E VSS/GND
D Q0 - DQ7 Data In/Data Out VCC W G Power (+5V) Write Enable Output Enable
1 4 15 16 17 18 19 20 DQ 1 DQ 2 DQ 3 DQ 4 G ND DQ 5 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2999.1
173
HM-6516/883 Functional Diagram
A LATCHED ADDRESS REGISTER 7 GATED RO W DECODER 12 8 128 x 128 MATRIX 1 OF 8 G G G W E L 1 6 1 6 16 16 16 16 16 16 GATED COLUMN DECODER 4 4 A 8 A A A LATCHED ADDRESS REGI STER A3 A2 A1 A0 8 DQ 0 T HRU DQ 7
A10 A9 A8 A7 A6 A5 A4
A 7
L
174
HM-6516/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for all Grades. . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC CERD IP Package . . . . . . . . . . . . . . . . 48oC/W 8oC/W CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W 12oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25953 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.4V to VCC Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . 2.0V to 4.5V Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. HM- 6516/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTE 1) CONDITIONS V CC = 4.5V IO = -1.0mA V CC = 4.5V IO = 3.2mA V CC = G = 5.5 V, VIO = GND or VCC V CC = 5.5V, V I = GND or VCC VCC = G = 5.5V, (Note 2) f = 1MHz, VI = GND or VCC V CC = 5.5V, HM-6516/883 E = VCC-0.3V, IO = 0mA, VI = GND or VCC V CC = 5.5V, HM-6516B/883 E = VCC -0.3V, IO = 0mA, VI = GND or VCC Data Retention Supply Current ICCDR V CC = 2.0V, HM-6516/883 E = VCC-0.3V, IO = 0mA, VI = GND or VCC V CC = 2.0V, HM-6516B/883 E = VCC-0.3V, IO = 0mA, VI = GND or VCC Functional Test NOTES : 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH 1.5V, and VOL 1.5V. FT VCC = 4.5V (Note 3) GR OU P A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE - 55oC TA +125oC - 55oC TA +125oC - 55oC TA +125oC MIN 2.4 -1.0 M AX 0.4 1.0 UNITS V V µA
PA RAME TER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Operating Supply Current S tandby Supply Current
SYMBOL VOH V OL IIOZ
II ICCOP ICCSB1
1, 2, 3 1, 2, 3 1, 2, 3
- 55oC TA +125oC - 55oC TA +125oC - 55oC TA +125oC
-1.0 -
1.0 10 100
µA mA µA
1, 2, 3
- 55oC TA +125oC
-
50
µA
1, 2, 3
- 55oC TA +125oC
-
50
µA
1, 2, 3
- 55oC TA +125oC
-
25
µA
7, 8A, 8B
- 55oC TA +125oC
-
-
-
175
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