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Details, datasheet, quote on part number:HM-6514
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Datasheet text preview:
TM
HM-6514
1024 x 4 CMOS RAM
Description
The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6514 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
March 1997
Features
· Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max · Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max · Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min · TTL Compatible Input/Output · Common Data Input/Output · Three-State Output · Standard JEDEC Pinout · Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max · 18 Pin Package for High Density · On-Chip Address Register · Gated Inputs - No Pull Up or Pull Down Resistors Required
Ordering Information
120n s HM3- 6514S-9 HM1- 6514S-9 24502BV A 8102402V A 200ns H M3 - 6 5 1 4 B - 9 H M1 - 6 5 1 4 B - 9 8 102404VA 300n s H M 3 -6514-9 H M 1 -6514-9 8102406V A HM 4-6514-B TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC -55oC to +125oC P ACKAG E PDIP CERDIP JAN# SMD # CLCC PKG. NO. E18.3 F18.3 F18.3 F18.3 J1 8 . B J18.B
Pinouts
HM-6514 (PDIP, CERDIP) TOP VIEW
A6 A5 A4 A3 A0 A1 A2 E GND 1 2 3 4 5 6 7 8 9 18 VCC 17 A7 16 A8 15 A9 14 DQ0 13 DQ1 12 DQ2 11 DQ3 10 W
HM-6514 (CLCC) TOP VIEW
VCC 18 A5 A6
PIN A E W D Q
DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output
A4 A3 A0 A1 A2 3 4 5 6 7
2
1
A7 17 16 A8 15 A9 14 DQ0 13 DQ1 12 DQ2 11 DQ 3
8 E
9 G ND
10 W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2995.1
HM-6514 Functional Diagram
LSB A9 A8 A7 A6 A5 A4
A LATCHED ADDRESS REGISTER L L 6 A 6 G A LATCHED ADDRESS REGISTER 4 A 4 G GATED COLUMN I/O SELECT 16 16 16 16 GATED ROW DECODER 64 x 64 MATRIX
64
LSB A2 A1 A0 A3
4
1 OF 4
E W DQ
2
HM-6514
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W PDIP Package . . . . . . . . . . . . . . . . . . . 75oC/W N/ A 33oC/W CLCC Package . . . . . . . . . . . . . . . . . . 90oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC JA JC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Ranges: HM-6514S-9, HM-6514B-9, HM-6514-9 . . . . . . . . -40oC to +85oC HM-6514B-8, HM-6514-8 . . . . . . . . . . . . . . . . . . -55oC to +125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
VCC = 5V ±10%; TA = -40oC to +85oC (HM-6514S-9, HM-6514B-9, HM-6514-9) TA = -55oC to +125oC (HM-6514B-8, HM-6514-8) LIMITS
SYMBOL ICCSB
PARAMETER Standby Supply Current HM -6514-9 HM -6514-8
MIN 2. 0 -1. 0 -1. 0 -0. 3 VCC -2.0 2. 4 VCC -0.4
M AX 25 50 7 15 25 +1.0 +1.0 0. 8 VCC +0.3 0. 4 -
UNITS µA µA mA µA µA V µA µA V V V V V
TEST CONDITIONS IO = 0mA, E = VCC -0.3V, VCC = 5.5V
I CCO P I CCDR
Operating Supply Current (Note 1) Data Retention Supply Current HM -6514-9 HM -6514-8
E = 1MHz, IO = 0mA, VI = GND, VCC = 5.5V IO = 0mA, VCC = 2.0V, E = VCC
V CCDR II IIOZ VI L VIH VOL VOH1 VOH2
Data Retention Supply Voltage Input Leakage Current Input/Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Note 2) TA = +25oC PARAMETER Input Capacitance (Note 2) Input/Output Capacitance (Note 2)
VI = VCC or GND, VCC = 5.5V VIO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 2.0mA, VCC = 4.5V IO = -1.0mA, VCC = 4.5V IO = -100µA, VCC = 4.5V
Capacitance
SYMBOL CI CIO NOTES:
M AX 8 10
UNITS pF pF
TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes.
3
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