|
Details, datasheet, quote on part number:HM-6508
| |
Datasheet text preview:
TM
HM-6508
1024 x 1 CMOS RAM
Description
The HM-6508 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On-Chip latches are provided for address, allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6508 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
March 1997
Features
· Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max · Low Power Operation . . . . . . . . . . . . . .20mW/MHz Max · Fast Access Time . . . . . . . . . . . . . . . . . . . . . 180ns Max · Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V Min · TTL Compatible Input/Output · High Output Drive - 2 TTL Loads · On-Chip Address Register
Ordering Information
PACKAGE PDIP CERDIP TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC 180ns HM3-6508B-9 HM1-6508B-9 250ns HM3-6508-9 HM1-6508-9 PKG. NO. E16.3 F16.3
Pinout
HM-6508 (PDIP, CERDIP) TOP VIEW
E1 A0 2 A1 3 A2 4 A3 5 A4 6 Q7 G ND 8 16 VCC 15 D 14 W 13 A9 12 A8 11 A7 10 A6 9 A5
PIN A E W D Q
DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved
File Number
2984.1
1
HM-6508 Functional Diagram
A5 A6 A7 A8 A9 A LATCHED ADDRESS REGISTER 5 A 5 32 D A GATED COLUMN DECODER A ND DATA I/O 5 A A 5 Q GATED ROW DECODER 32 32 x 32 MATRIX
A
W
E
LATCHED ADDRESS REGISTER
A0 A1 A2 A3 A4
NOTES : 1. All lines positive logic - active high. 2. Three-state buffers: A high output active. 3. Addr ess latches and gated decoders: latch on falling edge of E and gate on falling edge of E.
2
HM-6508
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . .1.5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) PDIP Package . . . . . . . . . . . . . . . . . . . 90oC/W N/A CERD IP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC JA JC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6508B-9, HM-6508-9 . . . . . . . . . . . . . . . . . . . - 40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6508B-9, HM-6508-9)
SYMBOL ICCSB ICCOP ICCDR PARAMETER Standby Supply Current Operating Supply Curr ent (Note 1) Data Retention Supply Current HM-6508B -9 HM-6508-9 MIN 2.0 -1.0 -1.0 -0.3 VCC -2.0 2.4 M AX 10 4 5 10 +1.0 +1.0 0.8 VCC +0.3 0.4 UNITS µA mA µA µA V µA µA V V V V VI = VCC or GND, V CC = 5.5V VO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 3.2mA, VCC = 4.5V IO = -0.4mA, VCC = 4.5V TEST CONDITIONS IO = 0mA, VI = VCC or GND, VCC = 5.0V E = 1MHz, IO = 0mA, VI = V CC or GND, V CC = 5.5V VCC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC
VCCDR II I OZ VIL V IH VOL VOH
Data Retention Supply Voltage Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Capacitance TA = +25oC
SYMBOL CI CO NOTES : 1. Typical derating 1.5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes 1. PARAMETER Input Capacitance (Note 2) Output Capacitance (Note 2) M AX 6 10 UNITS pF pF TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
AC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6508B-9, HM-6508-9)
H M-6508B -9 SYMBOL ( 1) ( 2) ( 3) TELQV TAVQV TELQX PARAMETER Chip Enable Access Time Address Access Time Chip Enable Output Enable Time MIN 5 M AX 180 180 120 HM-6508-9 MIN 5 M AX 250 250 160 UNITS ns ns ns TEST CONDITIONS (Notes 1, 3) (Notes 1, 3, 4) (Notes 2, 3)
3
|
|
