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Details, datasheet, quote on part number:HM-6504883
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Datasheet text preview:
HM-6504/883
March 1997
4096 x 1 CMOS RAM
Description
The HM-6504/883 is a 4096 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses, data input and data output allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6504/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
Features
· This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max · Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max · Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min · TTL Compatible Input/Output · Three-State Output · Standard JEDEC Pinout · Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max · 18 Pin Package for High Density · On-Chip Address Register · Gated Inputs - No Pull Up or Pull Down Resistors Required
Ordering Information
PACKAGE CERDIP TEMPERATURE RANGE -55oC to +125oC 200ns HM1-6504B/883 300ns HM1-6504/883 PKG. NO F18.3
Pinout
HM-6504/883 (CERDIP) TOP VIEW
A0 A1 A2 A3 A4 A5 Q W GND 1 2 3 4 5 6 7 8 9 18 VCC 17 A6 16 A7 15 A8 14 A9 13 A10 12 A11 11 D 10 E
PIN A E W D Q
DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
2993.1
6-134
HM-6504/883 Functional Diagram
LSB A8 A7 A6 A0 A1 A2
A LATCHED ADDRESS REGISTER L 6 GATED ROW DECODER G 64 G D Q A GATED COLUMN DECODER AND DATA I/O D Q Q A 64 x 64 MATRIX
64
A 6
D D Q
LATCH L
LATCH L
W
LATCH L
6 A L Q LATCHED ADDRESS REGISTER
6 A
E D
L LATCH
LSB A11 A5 A4 A3 A9 A10
NOTES: 1. All lines active high-positive logic. 2. Three-state Buffers: A high output active. 3. Control and Data Latches: L low Q = D and Q latches on rising edge of L. 4. Address Latches: Latch on falling edge of E. 5. Gated Decoders: Gate on rising edge of G.
6-135
HM-6504/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC +0.3V
TABLE 1. HM-6504/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER Output Low Voltage SYMBOL VOL (NOTE 1) CONDITIONS VCC = 4.5V, IOL = 2mA VCC = 4.5V, IOH = -1.0mA VCC = 5.5V, VI = GND or VCC VCC = 5.5V, VO = GND or VCC VCC = 2.0V, E = VCC, IO = 0mA VCC = 5.5V, (Note 2), E = 1MHz, IO = 0mA VCC = 5.0V, E = VCC -0.3V, IO = 0mA GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC 1, 2, 3 -55oC TA +125oC 25 7 µA mA MIN MAX 0.4 UNITS V
Output High Voltage
VOH
1, 2, 3
2.4
-
V µA µA
Input Leakage Current
II
1, 2, 3
-1.0
+1.0
Output Leakage Current
IOZ
1, 2, 3
-1.0
+1.0
Data Retention Supply Current
ICCDR
1, 2, 3
Operating Supply Current
ICCOP
Standby Supply Current
ICCSB
1, 2, 3
-55oC TA +125oC
-
50
µA
NOTES: 1. All voltage referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP.
6-136
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