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Details, datasheet, quote on part number:HM-6504
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Datasheet text preview:
TM
HM-6504
4096 x 1 CMOS RAM
Description
The HM-6504 is a 4096 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses, data input and data output allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6504 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
March 1997
Features
· Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max · Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max · Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min · TTL Compatible Input/Output · Three-State Output · Standard JEDEC Pinout · Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max · 18 Lead Package for High Density · On-Chip Address Register · Gated Inputs - No Pull Up or Pull Down Resistors Required
Ordering Information
120ns HM1-6504S-9 24501BVA 810240IVA 200ns HM3-6504B-9 HM1-6504B-9 8102403VA 300ns HM3-6504- 9 HM1-6504- 9 8102405VA HM4-6504- 9 TEMP. RANGE -40oC to +85oC -40oC to +85oC -40oC to+85oC PD IP CERDIP JAN # SMD # CL CC P ACKAGE PKG. NO. E18.3 F18.3 F18.3 F18.3 J18.B
Pinouts
H M-6504 (PDIP, CERDIP) TOP VIEW
A0 A1 A2 A3 A4 A5 Q W G ND 1 2 3 4 5 6 7 8 9 18 VCC 17 A6 16 A7 15 A8 14 A9 13 A10 12 A11 11 D 10 E VCC 18
PIN A E W D Q
DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output
A2 A3 A4 A5 Q 3 4 5 6 7
HM-6504 (CLCC) TOP VIEW
A1 A0 A6 17 16 15 14 13 12 8 W 9 G ND 10 E 11 D A7 A8 A9 A 10 A 11
2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2994.1
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HM-6504 Functional Diagram
LSB A8 A7 A6 A0 A1 A2
A LATCHED ADDRESS REGISTER L 6 A 6 GATED RO W DECODER G D D Q 6 A L LATCHED ADDRESS REGISTER 6 A Q A G 64 x 64 MATRIX
64
64 GATED COLUMN DECODER AND DATA I/O D L AT CH L Q Q A
D W
L AT CH L
LATCH L
E D
L Q L AT CH
LSB A11 A5 A4 A3 A9 A10
NOTES : 13. All lines active high-positive logic. 14. Three-state Buffers: A high output active. 15. Control and Data Latches: L low Q = D and Q latches on rising edge of L. 16. Addr ess Latches: Latch on falling edge of E. 17. Gated Decoders: Gate on rising edge of G.
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HM-6504
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V CC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
JC Thermal Resistance (Typical) JA CERD IP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W PDIP Package . . . . . . . . . . . . . . . . . . . 75oC/W N/A CLCC Package . . . . . . . . . . . . . . . . . . 90oC/W 33oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6504S-9, HM-6504B-9, HM-6504-9 . . . . . . . .-40oC to +85oC HM-6504B-8, HM-6504-8 . . . . . . . . . . . . . . . . . .-55oC to +125oC
DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6504B-9, HM-6504-9)
SYMBOL ICCSB PARAME TER Standby Supply Current HM-6504-9 HM-6504-8 ICCOP ICCDR Oper ating Supply Current (Note 1) Data Retention Supply Current HM-6504-9 HM-6504-8 MIN 2.0 -1.0 -1.0 -0.3 VCC -2.0 2.4 VCC -0.4 M AX 25 50 7 15 25 +1.0 +1.0 0.8 VCC +0.3 0.4 UNITS µA µA mA µA µA V µA µA V V V V V
TA = -55oC to +125oC (HM-6504B-8, HM-6504-8) TEST CONDITIONS IO = 0mA, E = VCC -0.3V, VCC = 5.5V E = 1MHz, IO = 0mA, VI = GND, VCC = 5.5V IO = 0mA, VCC = 2.0V, E = VCC
VCCDR II IOZ VIL VIH V OL V O H1 V O H2
Data Retention Supply Voltage Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Note 2)
VI = VCC or GND, VCC = 5.5V VO = VCC or GND, V CC = 5.5V VCC = 4.5V VCC = 5.5V IO = 2.0mA, VCC = 4.5V IO = -1.0mA, VCC = 4.5V IO = -100µA, VCC = 4.5V
Capacitance TA = +25oC
SYMBOL CI CO NOTES : 1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. PARAMETER Input Capacitance (Note 2) Output Capacitance (Note 2) M AX 8 10 UNITS pF pF TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
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