Details, datasheet, quote on part number: PENTIUMR.25MICRON
PartPENTIUMR.25MICRON
CategoryMicroprocessors => CISC => X86 Family
TitleX86 Family
DescriptionMobile Processor With Mmx(tm) Technology on 0.25 Micron
CompanyIntel Corporation
DatasheetDownload PENTIUMR.25MICRON datasheet
  

 

Features, Applications
MOBILE PENTIUM® PROCESSOR WITH MMXTM TECHNOLOGY ON 0.25 MICRON

Operating Frequency 166 MHz 200 MHz n 233 MHz 266 MHz Advanced Design Features Deeper Write Buffers Enhanced Branch Prediction Feature Virtual Mode Extensions 0.25 Micron Process Technology 1.8 V core supply (166/200/233 MHz) 2.0 V core supply (266 MHz) 2.5 V I/O Interface (166/200/233/266 MHz ) Internal Error Detection Features On-Chip Local APIC Controller Power Management Features System Management Mode Clock Control Fractional Bus Operation 166-MHz Core/66-MHz Bus 200-MHz Core/66-MHz Bus 233-MHz Core/66-MHz Bus 266-MHz Core/66-MHz Bus

Support for MMXTM Technology Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 32-Bit CPU with 64-Bit Data Bus Superscalar Architecture Enhanced pipelines Two Pipelined Integer Units Capable of 2 Instructions/Clock Pipelined MMX Technology Pipelined Floating-Point Unit Separate Code and Data Caches 16-Kbyte Code, 16-Kbyte Write Back Data MESI Cache Protocol 4-Mbyte Pages for Increased TLB Hit Rate 320-pin TCP or Mobile Module IEEE 1149.1 Boundary Scan

The mobile Pentium® processor with MMXTM technology on 0.25 micron extends the mobile Pentium processor family, providing additional performance for notebook applications. The mobile Pentium processor with MMX technology on 0.25 micron is compatible with the entire installed base of applications for MSDOS*, Windows*, OS/2*, and UNIX* and is one of the major microprocessors to support Intel MMX technology. Furthermore, the mobile Pentium processor with MMX technology on 0.25 micron has superscalar architecture which can execute two instructions per clock cycle, and enhanced branch prediction and separate caches also increase performance. The pipelined floating-point unit delivers workstation level performance. Separate code and data caches reduce cache conflicts while remaining software transparent. The mobile Pentium processor with MMX technology on 0.25 micron has 4.5 million transistors, is built on Intel's 0.25 micron manufacturing process technology and has full SL Enhanced power management features including System Management Mode (SMM) and clock control. The additional SL Enhanced features, 1.8/2.0V core operation along with 2.5V I/O buffer operation, a 320-pin Tape Carrier Package (TCP), and the Intel mobile module, make the mobile Pentium processor with MMX technology on 0.25 micron ideal for enabling mobile MMX technology designs. The mobile Pentium processor with MMX technology on 0.25 micron may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request.

MOBILE PENTIUM ® PROCESSOR WITH MMXTM TECHNOLOGY

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel' s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel may make changes to specifications and product descriptions at any time, without notice. The mobile Pentium® processor with MMXTM technology may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling or by visiting Intel' s website at http://www.intel.com

MOBILE PENTIUM® PROCESSOR WITH MMXTM TECHNOLOGY

PAGE 1.0. INTRODUCTION............................................ 4 2.0. MICROPROCESSOR ARCHITECTURE OVERVIEW.................................................... 4 2.1. Mobile Pentium ® Processor Family Architecture................................................ 5 2.2. Mobile Pentium ® Processor with MMX TM Technology................................................. 7 2.2.1. Full support for Intel MMX TM technology........................................... 7 2.2.2. Doubled code and data caches to 16K each..................................................... 7 2.2.3. Improved branch prediction.................. 7 2.2.4. Enhanced pipeline................................ 2.3 0.25 Micron Technology.................8 3.0. MOBILE PENTIUM ® PROCESSOR WITH MMXTM TECHNOLOGY PINOUT................... 8 3.1. Mobile Differences from Desktop................ 8 3.2. TCP Pinout and Pin Descriptions................ 9 3.2.1. TCP MOBILE PENTIUM ® PROCESSOR WITH MMXTM TECHNOLOGY PINOUT..................... 9 3.2.2. TCP MOBILE PENTIUM ® PROCESSOR WITH MMXTM TECHNOLOGY PIN CROSS REFERENCE..................................... 10 3.3. Design Notes............................................ 17 3.4. Quick Pin Reference................................. 17 3.5. Bus Frequency......................................... 26 3.6. Pin Reference Tables............................... 27 PAGE 3.7. Pin Grouping According to Function.......... 30 4.0. ELECTRICAL SPECIFICATIONS................ 31 4.1. Maximum Ratings..................................... 4.2. DC Specifications...................................... 31 4.2.1. POWER SEQUENCING..................... 4.3. AC Specifications...................................... 34 4.3.1. POWER AND GROUND.................... 34 4.3.2. DECOUPLING RECOMMENDATION 34 4.3.3. CONNECTION SPECIFICATIONS..... 4.3.4. AC TIMINGS FOR A 66-MHZ BUS.... 35 4.4. I/O Buffer Models...................................... 46 4.4.1. BUFFER MODEL PARAMETERS...... 49 4.4.2. SIGNAL QUALITY SPECIFICATION.. 51 4.4.3. CLOCK SIGNAL MEASUREMENT METHODOLOGY............................... 55 5.0. MECHANICAL SPECIFICATIONS............... 57 5.1. TCP Mechanical Diagrams....................... 58 6.0. THERMAL SPECIFICATIONS..................... 64 6.1. Measuring Thermal Values for TCP.......... 64 6.1.1. TCP Thermal Equations..................... 64 6.1.2. TCP Thermal Characteristics............. 64 6.1.3. TCP PC Board Enhancements........... 64 6.1.3.1. TCP STANDARD TEST BOARD CONFIGURATION............................. 65


 

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