Details, datasheet, quote on part number: PENTIUMRIIMMC-2
PartPENTIUMRIIMMC-2
CategoryMicroprocessors => CISC => X86 Family
TitleX86 Family
DescriptionMobile Module Connector 2 (mmc-2)
CompanyIntel Corporation
DatasheetDownload PENTIUMRIIMMC-2 datasheet
  

 

Features, Applications

INTEL PENTIUM® II PROCESSOR MOBILE MODULE : MOBILE MODULE CONNECTOR 2 (MMC-2)

Intel 443BX Host Bridge system controller DRAM controller supports EDO and SDRAM at 3.3V Supports PCI CLKRUN# protocol SDRAM clock enable support and self refresh of EDO or SDRAM during Suspend mode Compatible SMRAM (C_SMRAM) and Extended SMRAM (E_SMRAM) modes of power management; E_SMRAM mode supports write-back cacheable SMRAM MB 3.3V PCI bus control, Rev 2.1 compliant Active Thermal Feedback (ATF) sensing Internal A/D - digital signaling (SMBUS) across the module interface Programmable trip point interrupt or poll mode for temperature reading

Intel Mobile Pentium® II processor running at 233/266/300 MHz Second-level cache of pipeline burst SRAM Dedicated 64-bit wide bus for high speed data transfer 512K Byte cache data array Clock to BSRAM turns off when processor is in low power states Processor core voltage regulation supports input voltages from to 21V Above 80 percent peak efficiency Thermal transfer plate for heat dissipation Support single AGP-66 3.3V device

The Intel Pentium® II Processor Mobile Module is a small, highly integrated assembly containing an Intel Pentium II Mobile processor and its immediate system-level support. Specifically, the processor module contains a power supply for the processor's unique voltage requirements, a system Level 2 cache memory and the core logic required to bridge the processor to the standard system buses. The module interfaces electrically to its host system via a 3.3-volt PCI bus, a 3.3-volt memory bus and some Intel 443BX Host Bridge control signals.

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. © INTEL CORPORATION 1995 August 1998 Order Number: 243668-002

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel Pentium® II Processor Mobile Module may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling or by visiting Intel's website at http://www.intel.com Copyright © Intel Corporation 1998. * Third-party brands and names are the property of their respective owners.

PAGE 4.6. Processor Core Voltage Regulation............. 30 4.6.1. VOLTAGE REGULATOR EFFICIENCY........................................ 30 4.6.2. VOLTAGE REGULATOR CONTROL.. 31 4.6.2.1. Voltage Signal Definition and Sequencing.................................... 32 4.6.3. POWER PLANES: BULK CAPACITANCE REQUIREMENTS..... 34 4.6.4. SURGE CURRENT STUDY................. 34 4.6.4.1. Slew-Rate Control: Circuit Description..................................... 37 4.6.4.2. Under Voltage Lockout: Circuit Description..................................... 38 4.6.4.3. Over Voltage Lockout: Circuit Description..................................... 38 4.6.4.4. Over Current Protection: Circuit Description..................................... 39 4.7. Active Thermal Feedback............................ 39 4.8. Power Management..................................... 40 4.8.1. The Mobile Pentium® II Processor Clock Control Architecture.................... 40 4.8.2. NORMAL STATE.................................. 42 4.8.3. AUTO HALT STATE............................. 42 4.8.4. STOP GRANT STATE.......................... 42 4.8.4.1. Quick Start State............................ 43 4.8.5. HALT/GRANT SNOOP STATE............ 43 4.8.6. SLEEP STATE...................................... 43 4.8.7. DEEP SLEEP STATE........................... 44 4.8.8. CURRENTLY SUPPORTED CLOCK STATES................................................ 44 4.8.9. OPERATING SYSTEM IMPLICATIONS OF THE QUICK START AND SLEEP STATES................................................ 44 4.9. Typical POS/STR Power.............................. 45 5.0. MECHANICAL REQUIREMENTS.................. 45 5.1. Module Dimensions...................................... 45 5.1.1. BOARD AREA...................................... 5.1.2. MMC-2 PIN 1 LOCATION..................... 46 5.1.3. PRINTED CIRCUIT BOARD THICKNESS......................................... 47 5.1.4. HEIGHT RESTRICTIONS.................... 47 3

1.0. INTRODUCTION............................................... 5 1.1. Pentium® II Processor Mobile Module Terminology................................................... 5 1.2. Revision History............................................. 6 2.0. ARCHITECTURE OVERVIEW.......................... 6 3.0. MODULE CONNECTOR INTERFACE............. 8 3.1. Signal Definitions............................................ 8 3.1.1. SIGNAL LIST.......................................... 9 3.1.2. MEMORY (109 SIGNALS).................... 10 3.1.3. AGP (60 SIGNALS).............................. 11 3.1.4. PCI (58 SIGNALS)................................ 3.1.5. PROCESSOR/PIIX4E SIDEBAND (8 SIGNALS)......................................... 14 3.1.6. POWER MANAGEMENT/ GEYSERVILLE (11 SIGNALS)............ 15 3.1.7. CLOCK (9 SIGNALS)........................... 16 3.1.8. VOLTAGES (54 SIGNALS).................. 17 3.1.9. ITP/JTAG (9 SIGNALS)........................ 18 3.1.10. MISCELLANEOUS (82 SIGNALS)..... 19 3.2. Connector Pin Assignments......................... 20 3.3. Pin and Pad Assignments............................ 23 4.0. FUNCTIONAL DESCRIPTION....................... 24 4.1. Intel Mobile Module...................................... 4.2. L2 Cache...................................................... 4.3. 443BX Host Bridge System Controller......... 24 4.3.1. MEMORY ORGANIZATION................. 25 4.3.2. RESET STRAP OPTIONS................... 25 4.3.3. PCI INTERFACE................................... 26 4.3.4. AGP INTERFACE................................. 26 4.4. Electrical Requirements............................... 4.4.1. DC REQUIREMENTS........................... 4.4.2. AC REQUIREMENTS........................... 4.4.3. AC REQUIREMENTS........................... 28 4.4.3.1. System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines............... ® 4.5. Pentium II Processor Mobile Module Signal Termination....................................... 30


 

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