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Part: 74LVC125A
Category:
Logic
Description: 3.3V CMOS Quadruple Bus Buffer Gate With 3-STATE Outputs And 5V Tolerant I/o
Company: Integrated Device Technology, Inc.
Datasheet: Download 74LVC125A datasheet File size : 291 kB
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IDT74LVC125A 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
· 0.5 MICRON CMOS Technology · ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) · VCC = 3.3V ± 0.3V, Normal Range · VCC = 2.7V to 3.6V, Extended Range · CMOS power levels (0.4µ W typ. static) µ · Rail-to-Rail output swing for increased noise margin · All inputs, outputs, and I/Os are 5V tolerant · Supports hot insertion · Available in SOIC, SSOP, and TSSOP packages
IDT74LVC125A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
The LVC125A quadruple bus buffer gate is built using advanced dual metal CMOS technology. The LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the associated outputenable (OE) input is high. To ensure the high impedance state during power up or power down, OE should be tied to Vcc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment. The LVC125A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
· High Output Drivers: ±24mA · Reduced system switching noise
· 5V and 3.3V mixed voltage systems · Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1OE
1
3OE
10
2 1A
3 1Y 3A
9
8 3Y
2OE
4
4OE
13
5
2A
6
12 2Y 4A
11
4Y
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2 0 0 0 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4557/1
IDT74LVC125A 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1OE 1A 1Y 2OE 2A 2Y
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND Max 0.5 to +6.5 65 to +150 50 to +50 50 ±100 Unit V °C mA mA mA
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC
4OE 4A 4Y 3OE 3A 3Y
TSTG IOUT IIK IOK ICC ISS
GND
NOTE: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
SOIC/ SSOP/ TSSOP TOP VIEW
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N CO U T CI / O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 5.5 6.5 Max. 6 8 8 Unit pF pF pF
NOTE: 1 . As applicable to the device type.
PIN DESCRIPTION
Pin Names xOE xA xY Data Inputs 3-State Outputs Description Output-Enable Inputs (Active LOW)
FUNCTION TABLE (EACH BUFFER)(1)
Inputs xOE L L H
NOTE: 1 . H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance
Outputs xA H L X xY H L Z
2
IDT74LVC125A 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40°C to +85°C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = 18mA VCC = 3.3V VCC = 3.6V, VIN = GND or VCC -- -- -- -- -- 0.7 100 -- ±50 1.2 -- 10 µA V mV µA VCC = 3.6V VO = 0 to 5.5V -- -- ±10 µA Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 ±5 µA V Unit V
Quiescent Power Supply Current Variation
One input at VCC - 0.6V, other inputs at VCC or GND
--
--
500
µA
NOTE: 1 . Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = 0.1mA IOH = 6mA IOH = 12mA Min. VCC 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1 . VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = 40°C to + 85°C.
3
IDT74LVC125A 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V±0.2V Symbol CPD Parameter Power Dissipation Capacitance per gate Test Conditions CL = 0pF, f = 10Mhz Typical 11.3 VCC = 3.3V±0.3V Typical 15 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xA to xY Output Enable Time xOE to xY Output Disable Time xOE to xY Output Skew(2) Min. 1 1 1 -- Max. 6.3 7.4 5.6 -- VCC = 2.7V Min. -- -- -- -- Max. 5.5 6.6 5 -- VCC = 3.3V ± 0.3V Min. 1 1 1 -- Max. 4.8 5.4 4.6 1 Unit ns ns ns ns
NOTES: 1 . See TEST CIRCUITS AND WAVEFORMS. TA = 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC125A 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 VCC(2)= 3.3V±0.3V & 2.7V 6 2.7 1.5 300 300 50 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
Propagation Delay
LVC QUAD Link
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
LVC QUAD Link
VIN D.U.T. RT
VOUT
500 CL
LVC QUAD Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1 . Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. 2 . Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.
NOTE: 1 . Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT SYNCHRONOUS CONTROL ASYNCHRONOUS CONTROL
tSU
tH
tREM
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC QUAD Link
Set-up, Hold, and Release Times
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT
LVC QUAD Link
OUTPUT 1
tSK (x)
tSK (x)
VT
OUTPUT 2 tPLH2 tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC QUAD Link
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
Pulse Width
5
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