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Details, datasheet, quote on part number:PEELTM18LV8Z
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Datasheet text preview:
Commercial/Industrial
PEELTM 18LV8Z-15 / I-15
CMOS Programmable Electrically Erasable Logic Device Features
· Low Voltage, Ultra Low Power Operation - VCC = 2.7 to 3.6 V - ICC = 5 µA (typical) at standby - ICC = 1.5 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JEDSD8-A) - 5 Volts tolerant inputs and I/O's CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Application Versatility - Replaces random logic - Super set of standard PLDs - Pin-to-pin compatible with 16V8 - Ideal for battery powered systems - Replaces expensive oscillators · · Architectural Flexibility - Enhanced architecture fits in more logic - 113 product terms x 36 input AND array - 10 inputs and 8 I/O pins - 12 possible macrocell configurations - Asynchronous clear, Synchronous preset - Independent output enables - Programmable clock; pin 1 or p-term - Programmable clock polarity - 20 Pin DIP/SOIC/TSSOP and PLCC - Schmitt triggers on clock and data inputs Schmitt Trigger Inputs - Eliminates external Schmitt trigger devices - Ideal for encoder designs
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General Description
The PEEL18LV8Z is a Programmable Electrically Erasable Logic (PEEL) SPLD (Simple Programmable Logic Device) that operates over the supply voltage range of 2.7V-3.6V and features ultra-low, automatic "zero" power-down operation. The PEEL18LV8Z is logically and functionally similar to ICT's 5V PEEL18CV8 and PEEL18CV8Z. The "zero power" (25 µA max. ICC) power-down mode makes the PEEL18LV8Z ideal for a broad range of batterypowered portable equipment applications, from hand-held meters to PCMCIA modems. EE-reprogrammability provides both the convenience of fast reprogramming for product development and quick product personalization in manufacturing, including Engineering Change Orders. The differences between the PEEL18LV8Z and PEEL18CV8 include the addition of programmable clock polarity, p-term clock, and Schmitt trigger input buffers on all inputs, including the clock. Schmitt trigger inputs allow direct input of slow or noisy signals. Like the PEEL18CV8, the PEEL18LV8Z is a logical superset of the industry standard PAL16V8 SPLD. The PEEL18LV8Z provides additional architectural features that allow more logic to be incorporated into the design. ICT's JEDEC file translator allows easy conversion of existing 20 pin PLD designs to the PEEL18LV8Z architecture without the need for redesign. The PEEL18LV8Z architecture allows it to replace over twenty standard 20-pin DIP, SOIC, TSSOP and PLCC packages Pin Configuration.
C L K M U X (O p t io n a l)
I/C L K 1 I I I I I I I I GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC I/O I/O I/O I/O I/O I/O I/O I/O I
I/C L K 1 I I I I I I I I GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VC C I/O I/O I/O I/O I/O I/O I/O I/O I
ª
D IP
I/C L K 1 V CC I/O I/O I/O
TSS O P
I/C L K 1 3 I I I I I 4 5 6 7 8 9 10 11 12 13 2 1 20 19 18 17 16 15 14 I/O I/O I/O I/O I/O I I I I I I I I GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC I/O I/O I/O I/O I/O I/O I/O I/O I
I
GN D
I
I/O
P L C C -J
I/O
S O IC
Figure 1 - Pin Configuration
Figure 2 - Block Diagram
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PEEL 18LV8Z-15/I-15
(OPTIONAL)
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35
112 0 1 2
ASYNCHRONOUS CLEAR (TO ALL MACROCELLS)
9
I/CLK
1
10 11
MACRO CELL
19
I/O
20
MACRO CELL
18
I/O
I
2
21 22
MACRO CELL
33
17
I/O
I
3
34 35
MACRO CELL
48
16
I/O
I
4
49 50
MACRO CELL
65
15
I/O
I
5
66 67
I/O MACRO CELL
82
14
I
6
83 84
MACRO CELL
97
13
I/O
I
7
98 99
MACRO CELL
110
12
I/O
I I
8
111
9
SYNCHRONOUS PRESET (TO ALL MACROCELLS) 11 I
Figure 3 - PEEL18LV8Z Logic Array Diagram
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PEEL 18LV8Z-15/I-15 Function Description
The PEEL18LV8Z implements logic functions as sum-ofproducts expressions in a programmable-AND/fixed-OR logic array. Programming the connections of input signals into the array creates user-defined functions. Userconfigurable output structures in the form of I/O macrocells further increase logic flexibility. Architecture Overview The PEEL18LV8Z architecture is illustrated in the block diagram of Figure 2. Ten dedicated inputs and 8 I/Os provide up to 18 inputs and 8 outputs for creation of logic functions. At the core of the device is a programmable electrically erasable AND array that drives a fixed OR array. With this structure, the PEEL18LV8Z can implement up to 8 sum-of-products logic expressions. Associated with each of the 8 OR functions is an I/O macrocell that can be independently programmed to one of 12 different configurations. The programmable macrocells allow each I/O to be used to create sequential or combinatorial logic functions of active-high or active-low polarity, while providing three different feedback paths into the AND array. AND/OR Logic Array The programmable AND array of the PEEL18LV8Z (shown in Figure 3) is formed by input lines intersecting product terms. The input lines and product terms are used as follows: · 36 Input Lines: - 20 input lines carry the true and complement of the signals applied to the 10 input pins - 16 additional lines carry the true and complement values of feedback or input signals from the 8 I/Os 113 product terms: - 102 product terms are used to form sum of product functions - 8 output enable terms (one for each I/O) - 1 global synchronous preset term - 1 global asynchronous clear term - 1 programmable clock term When programming the PEEL18LV8Z, the device programmer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array. The device is configured to perform the user-defined function by programming selected connections in the AND array. (Note that PEEL device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function). Variable Product Term Distribution The PEEL18LV8Z provides 113 product terms to drive the 8 OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see Figure 3). This distribution allows optimum use of the device resources. Programmable I/O Macrocell The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to configure each output independently lets you to tailor the configuration of the PEEL18LV8Z to the precise requirements of your design. Macrocell Architecture Each I/O macrocell, as shown in Figure 4, consists of a Dtype flip-flop and two signal-select multiplexers. The four EEPROM bits controlling these multiplexers determine the configuration of each macrocell. These bits determine output polarity, output type (registered or non-registered) and input-feedback path (bi-directional I/O, combinatorial feedback). Refer to Table 1 for details. Equivalent circuits for the twelve-macrocell configurations are illustrated in Figure 5. In addition to emulating the four PAL-type output structures (configurations 3, 4, 9, and 10), the macrocell provides eight additional configurations. When creating a PEEL device design, the desired macrocell configuration is generally specified explicitly in the design file. When the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the JEDEC programming file. Output Type The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flip-flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register is set HIGH at the next rising edge of the clock input. Satisfying
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At each input-line/product-term intersection, there is an EEPROM memory cell that determines whether or not there is a logical connection at that intersection. Each product term is essentially a 36-input AND gate. A product term that is connected to both the true and complement of an input signal will always be FALSE and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a "don't care" state exists and that term will always be TRUE.
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