Details, datasheet, quote on part number: HYS72V32301GR-7-C2
CategoryMemory => DRAM => SDR SDRAM => Modules => 256 MB
Description128MB - 2GB, 168pin
CompanyInfineon Technologies Corporation
DatasheetDownload HYS72V32301GR-7-C2 datasheet
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Features, Applications

HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules V 168-pin Registered SDRAM Modules PC133 128 MByte Module PC133 256 MByte module PC133 512 MByte Module PC133 1 GByte Module PC133 2 GByte Module

168-pin Registered 8 Byte Dual-In-Line SDRAM Module for PC and Server main memory applications One bank x 72, two bank 72 and x 72 organization Optimized for ECC applications with very low input capacitances JEDEC standard Synchronous DRAMs (SDRAM) Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) Single 0.3 V) power supply Auto Refresh (CBR) and Self Refresh Performance: speed grade

fCK tCK tAC fCK tCK tAC Clock Frequency (max.) = 3 Clock Cycle Time (min.) = 3 Clock Access Time (min.) @ CL= 3 Clock Frequency (max.) = 2 Clock Cycle Time (min.) = 2 Clock Access Time (min.) @ CL= 2

Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) All inputs and outputs are LVTTL compatible Serial Presence Detect with E2PROM Utilizes SDRAMs in TSOPII-54 packages with registers and PLL. Card Size: 133.35 mm with Gold contact pads and max. 6.80 mm thickness (JEDEC MO-161) These modules all fully compatible with the current industry standard PC133 and PC100 specifications


The HYS 72Vxx3xxGR-7 and -7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) organized 72 and x 72 high speed memory arrays designed with Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacitive loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial E2PROM using the I 2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface 133.35 mm long footprint.

HYS 72V16300GR-7.5-C HYS 72V16300GR-7.5-E HYS 72V16301GR-7.5-C2 HYS 72V32301GR-7.5-C2 HYS 72V32300GR-7.5-C2 HYS 72V32300GR-7.5-D HYS 72V64300GR-7.5-C2 HYS 72V64300GR-7.5-D PC133R-333-542-B2 one bank 128 MB Reg. DIMM PC133R-333-542-B2 one bank 128 MB Reg. DIMM PC133R-333-542-B2 one bank 256 MB Reg. DIMM PC133R-333-542-AA one bank 256 MB Reg. DIMM PC133R-333-542-B2 one bank 512 MB Reg. DIMM 64 MBit (x4) 128 MBit (x8) 128 Mbit (x4) 256 Mbit (x8) 256 MBit (x4) 256 MBit (x4, stacked) 3) 512 MBit (x4) 512 MBit (x4, stacked) 3)

HYS 72V128320/1GR-7.5-C2 PC133R-333-542-B2 two banks 1 GByte Reg. DIMM HYS 72V128320/1GR-7.5-D HYS 72V128300GR-7.5-A HYS 72V256320/1GR-7.5-A PC133R-333-542-B2 one bank 1 GByte Reg. DIMM PC133R-333-542-B2 two banks 2 GByte Reg. DIMM

HYS 72V16300GR-7-E HYS 72V16301GR-7-C2 HYS 72V32301GR-7-C2 HYS 72V32300GR-7-D HYS 72V64300GR-7-D HYS 72V128320/1GR-7-D HYS 72V128300GR-7-A HYS 72V256320/1GR-7-A PC133R-222-542-B2 one bank 128 MB Reg. DIMM PC133R-222-542-B2 one bank 128 MB Reg. DIMM PC133R-222-542-B2 one bank 256 MB Reg. DIMM PC133R-222-542-AA one bank 256 MB Reg. DIMM PC133R-222-542-B2 one bank 512 MB Reg. DIMM PC133R-222-542-B2 two banks 1 GByte Reg. DIMM PC133R-222-542-B2 one bank 1 GByte Reg. DIMM PC133R-222-542-B2 two banks 2 GByte Reg. DIMM 64 MBit (x4) 128 MBit (x8) 128 Mbit (x4) 256 Mbit (x8) 256 MBit (x4) 256 MBit (x4, stacked) 3) 512 MBit (x4) 512 MBit (x4, stacked) 3)

Notes: 1.) All part numbers end with a place code, designating the die revision of the components used on the Registered DIMM module. Consult factory for current revision. Example: HYS 64V32300GR-7.5-D, indicating Rev.D dies are used for 256Mbit SDRAM components. 2.) The Compliance Code is printed on the modules labels and describes speed sort of the modules, latencies, access time from clock,SPD revision and Raw Card version acording to the actual JEDEC standard. 3.) Modules with stacked components are available in two version, with components stacked using a soldering stacking technique (f.e. HYS72V128320GR-7.5 ) and an welding technique developed by INFINEON Technologies (f.e. HYS72V128321GR-7.5).

- DQ63 Address Inputs (A12 is used for 256Mbit based modules only) Bank Selects Data Input/Output - CS3 REGE*) Data Mask Chip Select Register Enable "H" or N.C = registered mode "L" = buffered mode Power 3.3 V) Ground Clock for Presence Detect Serial Data Out No Connection

Check Bits Row Address Strobe Column Address Strobe Read/Write Input Clock Enable Clock Input

Note : To confirm to this specification, motherboards must pull this pin to high state or no connect.


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