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Details, datasheet, quote on part number:M2006-01PB
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Datasheet text preview:
Integrated Circuit Systems, Inc.
Product Brief
M2006-01
VCSO FREQUENCY TRANSLATOR
GENERAL DESCRIPTION
The M2006-01 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for reference clock frequency translation and jitter attenuation in a high-speed data communications system. The M2006-01 includes a unique clock add/drop feature that enables data FIFO overflow control. Internal divider ratios are user selectable, and external loop filter components allow tailoring of the PLL loop response.
PIN ASSIGNMENT (9 x 9 mm SMT)
nDIF_REF1 nDIF_REF0 DIF_REF0 REF_CLK REF_SEL S_LOAD S_DATA 20 GND VCC 19 18 17 16
27
26
24
23
25
DIR_REF1 REF_SEL0 ADD_CLK DROP_CLK PSL
28 29 30 31 32 33 34 35 36 5 6 7 1 2 3 4 8 9
22
21
S_CLOCK P1 nFOUT0 FOUT0 GND NFOUT1 FOUT1 VCC GND
M2006-01
(Top View)
15 14 13 12 11 10
F EATURE S
· Integrated SAW (surface acoustic wave) delay line · Output clock center frequencies from 75 to 700
MHz (Specify center frequency at time of order)
VCC DNC DNC DNC
nOP_OUT
· · · · ·
transients and assures MTIE compliance for GR-253 (SONET) and G.813 (SDH) Clock Add/Drop feature enables data FIFO centering Universal differential reference inputs support LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL Power-up default divider ratios suitable for most optical networking applications Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
Example Input / Output Frequency Combinations
Input Clock (MHz) 19.44 19.53125 VCSO Freq 1 (MHz) 622.08 625.00 Output Freq (MHz) 622.08 155.52 156.25 Application OC-12/48 Gigabit Ethernet
1.Specify VCSO center frequency at time of order
BLOCK DIAGRAM
R LOOP CLOOP RPOST CPOST CPOST R LOOP CLOOP OP_OUT RPOST nOP_OUT nV C VC
Exte rnal Loop Filter Components
M2006-01
MUX
OP_IN Phase Detector
nOP_IN
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_CLK REF_SEL1:0
2
RIN
SAW Delay Line
00
R Divider
R = 1-511 Power-Up Default = 1 RIN
01 1X
Loop Filter Amplifier
Phase Shifter
VCSO
M Divider
M = 3-1024 Power-Up Default = 32
OP_OUT
nOP_IN
GND
GND
GND
OP_IN
nVC
VC
· Low phase jitter 0.5ps RMS, typical (12kHz-20MHz) · Internal protection switch circuit absorbs input phase
S_DATA S_CLK S_LOAD
FOUT0 nFOUT0 P Divider
P = 1 ( P1 = 0 ) or 4 ( P1 = 1 )
Serial Configuration Register
FOUT1 nFOUT1
PSL
ADD_CLK
DROP_CLK
P1
MNC 2006-01 Rev 1.0
M2006-01 VCSO Frequency Translator
Revision 112602
I n t e g r a t e d Circuit Systems, Inc. Communications Modules
www.icst.com/comm-modules
tel (508) 852-5400
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