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Details, datasheet, quote on part number:M2005-01-622.0800
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Datasheet text preview:
Micro Networks
An Integrated Circuit Systems Company
M2005-01
Preliminary Specifications
M2005-01
Frequency Translator
DESCRIPTION
The M2005-01 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for reference clock frequency translation and jitter attenuation in a high speed data communications system. The device is similar to the M2004-01 but includes a frequency hold-over feature that allows the output frequency to be maintained in the event of a disrupted input reference clock. Internal divider ratios are user selectable, and external loop filter components allow tailoring of the PLL loop response.
FEATURES
ABSOLUTE MAX RATINGS Inputs, VI : ....... -0.5 to VCC+0.5V Output, VO : ....... -0.5 to VCC+0.5V Supply Voltage, VCC : ......... 4.6 V Storage Temperature, TSTO : .... -45°C to +100°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Integrated SAW (surface acoustic wave) delay line Output clock frequency up to 700MHz (Consult factory for available frequencies) RMS Jitter <1ps RMS (12kHz-80MHz) Hold-over error +10ppm max Single 3.3V supply Small 9x9mm SMT package includes SAW device Ideal for OC-48, SDH-12, 10GbE transmit clock
ISO 9001 Registered
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
1
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company FUNCTIONAL BLOCK DIAGRAM
M2005-01
Preliminary Specifications
The internal PLL will adjust the VCSO output frequency to be M (feedback divider) divided by P (input divider) times the selected input reference clock frequency. Note that the ratio of M/P times input frequency must be such that it falls within the "lock" range of the VCSO. The M divider (17-bits) can be programmed for a maximum value of 131,071 and a minimum value of 4. The P divider (9-bits) can be set to a maximum value of 511 and a minimum value of 1. The N output divider can be programmed to divide the VCSO output frequency by 1, or 4 and provide a 50% output duty cycle. The M2005-01 is serially programmed via a 3 wire interface. Figure 1 shows the timing diagram for serial programming. The relationship between the VCSO frequency, the M & P dividers, and the input REF_CLK is defined as follows: F VCSO = F REF_CLK x M P When the N output divider is included, the
complete relationship for the output frequency is defined as: FOUT = F VCSO = F REF_CLK x M N NxP The N1 input can be hard wired to set the N divider to a specific state that will automatically occur during power-up. Serial operation occurs when S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW to- HIGH. The M divider and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. When the HOLD input is asserted the M2005-01 will revert back to the initial accuracy of the VCSO and remain at that frequency until the HOLD signal is returned LOW.
RLOOP
CLOOP
RPOST CPOST CPOST
Ex ternal Loop Filter Components
RLOOP
CLOOP
RPOST nOP_OUT nVC VC 0 Frequency Hold 1 Phase Shifter VCSO SAW Delay Line
M2005-01
MUX 1 0
OP_IN
nOP_IN OP_OUT
REF_CLK1 REF_CLK0 REF_SEL
Phase Detector RIN
RIN
Loop Filter Amplifier M Divider M = 3-1023
S_DATA S_CLK S_LOAD nP_LOAD
P Divider P = 1 or 4
FOUT nFOUT
Serial / Parallel Configuration Register
6 M5:0
P1
HOLD
MR
FIGURE 1
S_DATA Low Low Null N1 N0 Null Null Null M5 M4 M3 M2 M1 M0
S_CLK
S_LOAD
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
2
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company FUNCTIONAL DESCRIPTION LOOP FILTER FIGURE 2
Rloop OP_IN Cloop
M2005-01
Preliminary Specifications
The M2005-01 requires the use of an external loop filter via the provided filter pins. Due to the differential design, the implementation requires two identical RC filters as shown in Figure 2.
Rpost nVc Cpost
nOP_OUT OP_OUT Cpost nOP_IN Rloop Cloop Rpost Vc
TABLE 1. RECOMMENDED LOOP FILTER VALUES REF_CLK Frequency 19.44MHz VCSO Frequency 622.0800MHz M N FOUT Rloop Cloop Rpost Cpost
32
1
622.0800MHz
5k
1MF
50k
100pf
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
3
fax: 508-852-8456
www.micronetworks.com
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