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Details, datasheet, quote on part number:M2004-01-622.0800
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Datasheet text preview:
Micro Networks
An Integrated Circuit Systems Company
M2004-01
Preliminary Specifications
M2004-01
Frequency Synthesizer
DESCRIPTION
The M2004-01 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Translator in a 9mm x 9mm surface mount package. The internal high "Q" SAW filter provides low jitter signal performance and determines the maximum output frequency of the VCSO. A programmable output divider can divide the VCSO frequency to achieve an output as low as 38.88MHz.
FEATURES
Output Clock Frequency up to 700MHz Differential LVPECL Outputs Internal Low-jitter SAW-based Oscillator Intrinsic Jitter <1ps rms (12kHz - 20MHz) Jitter Attenuation of Input Reference Clock Dual Input MUX Parallel Programming Tunable Loop Filter Response Differential LVPECL Outputs 3.3V Operation Small 9mm x 9mm SMT Package
The input to the Frequency Translator is provided by selecting between one of two output reference clocks. The output frequency is an integer multiple of the input reference frequency. Parallel and serial control of the output and feedback dividers is provided via the configuration logic. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock. The M2004-01 is available at SONET/SDH and 10GbE frequencies up to 700MHz.
APPLICATIONS
ABSOLUTE MAX RATINGS Inputs, VI : ....... -0.5 to VCC+0.5V Output, VO : ....... -0.5 to VCC+0.5V Supply Voltage, VDD : ......... 4.6 V Storage Temperature, TSTO : .... -45°C to +100°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
SONET / SDH / 10GbE System Synchronization Add / Drop Muxes, Access and Edge Switches Line Card System Clock Cleaner / Translator Optical Module Clock Cleaner / Translator
ISO 9001 Registered
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
1
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company FUNCTIONAL BLOCK DIAGRAM
M2004-01
Preliminary Specifications
The internal PLL will adjust the VCSO output frequency to be M times the selected input reference clock frequency. Note that the product of M x input frequency must be such that it falls within the "lock" range of the VCSO. The N output divider can be programmed to divide the VCSO output frequency by 1, 2, 4, or 8 and provide a 50% output duty cycle.
RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP RPOST nOP_OUT nVC VC SAW Delay Line
The relationship between the VCSO frequency, the input REF_CLK , and the M divider is defined as follows: F VCSO = F REF_CLK x M When the N output divider is included, the complete relationship for the output frequency is defined as: FOUT = F VCSO = F REF_CLK x M N N The M value and the required logic states of M0 through M5 are shown in Table 5B, Programmable VCSO Frequency Function Table. (i.e. For an output frequency of 622.0800MHz and an input frequency of 19.44MHz the M value would be 32 and the N value would be 1. Similarly, for an output frequency of 311.04MHz and an input frequency of 19.44 MHz the M value would be 32 and the N value would be 2.) Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divider and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK.
Ex ternal Loop Filter Components
M2004-01
MUX
OP_IN
nOP_IN OP_OUT
REF_CLK1 REF_CLK0 REF_SEL
Phase Detector RIN
RIN
1 0 Loop Filter Amplifier M Divider M = 3-1023 N Divider N = 1,2,4,8 Serial / Parallel Configuration Register Phase Shifter VCSO
S_DATA S_CLK S_LOAD nP_LOAD
FOUT nFOUT
6 M5:0
2 N1:0
MR
The M2004-01 supports both parallel and serial operating modes for programming the M divider and N output divider. Figure 1 shows the timing diagram for each mode. In the parallel mode the nP_LOAD input is initially LOW. The data on inputs M0 through M5 and N0 and N1 is passed directly to the M divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up.
FIGURE 1
S_DATA
Low Low Null
N1
N0 Null Null Null M5
M4
M3
M2
M1
M0
S_CLK
S_LOAD
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
2
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company FUNCTIONAL DESCRIPTION LOOP FILTER FIGURE 2
Rloop OP_IN Cloop
M2004-01
Preliminary Specifications
The M2004-01 requires the use of an external loop filter via the provided filter pins. Due to the differential design, the implementation requires two identical RC filters as shown in Figure 2.
Rpost nVc Cpost
nOP_OUT OP_OUT Cpost nOP_IN Rloop Cloop Rpost Vc
TABLE 1. RECOMMENDED LOOP FILTER VALUES REF_CLK Frequency 19.44MHz VCSO Frequency 622.0800MHz M N FOUT Rloop Cloop Rpost Cpost
32
1
622.0800MHz
5k
1MF
50k
100pf
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
3
fax: 508-852-8456
www.micronetworks.com
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