Details, datasheet, quote on part number: ICS180M-03T
PartICS180M-03T
CategoryTiming Circuits => Clock Generators
DescriptionLow EMI Single-Output Clock
The ICS180-03 generates a low EMI output clock from
a clock or crystal input. The device uses ICS’
proprietary mix of analog and digital Phase Locked
Loop (PLL) technology to spread the frequency
spectrum of the output, thereby reducing the frequency
amplitude peaks by several dB.
The ICS180-03 offers down spread selection of -1.25%
and -3.75%. Refer to the MK1714-01/02 for the widest
selection of input frequencies and multipliers.
ICS offers a complete line of EMI reducing clock
generators. Consult us when you need to remove
crystals and oscillators from your board.
Features
• Pin and function compatible to Cypress W180-03
• Packaged in 8-pin SOIC
• Provides a spread spectrum output clock
• Accepts a clock input and provides same frequency
dithered output
• Input frequency of 15 to 28 MHz
• Peak reduction by 7dB - 14dB typical on 3rd - 19th
odd harmonics
• Spread percentage selection for -1.25% and -3.75%
• Operating voltage of 3.3 V and 5 V
• Advanced, low-power CMOS process
CompanyIntegrated Circuit System
DatasheetDownload ICS180M-03T datasheet
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Packages8-pin SOIC
  

 

Features, Applications
Description

The ICS180-03 generates a low EMI output clock from a clock or crystal input. The device uses ICS' proprietary mix of analog and digital Phase Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. The ICS180-03 offers down spread selection of -1.25% and -3.75%. Refer to the MK1714-01/02 for the widest selection of input frequencies and multipliers. ICS offers a complete line of EMI reducing clock generators. Consult us when you need to remove crystals and oscillators from your board.

Features

Pin and function compatible to Cypress W180-03 Packaged in 8-pin SOIC Provides a spread spectrum output clock Accepts a clock input and provides same frequency dithered output

Input frequency to 28 MHz Peak reduction - 14dB typical - 19th

Spread percentage selection for -1.25% and -3.75% Operating voltage 3.3 V and 5 V Advanced, low-power CMOS process

FS1 SSON# SS% PLL Clock Synthesis and Spread Spectrum Circuitry
SS% (Pin 0 1 Spread Direction Down Spread Percentage -1.25% -3.75%
0 = connect to GND 1 = connect directly to VDD Note: SS% pin has an internal pull-up resistor
Input Output Power Input Output Power Input

Crystal or Clock Input. Crystal output. Float for a clock input. Connect to ground. Select pin for spread amount. See table above. Internal pull-up resistor. Spread spectrum clock output per table above. Connect 5 V. Select pin for input frequency. See table above. Internal pull-up resistor. Spread Spectrum Control. This pin enables spread spectrum when low. Internal pull-down resistor.

The ICS180-03 requires a minimum number of external components for proper operation.

For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI the 33 series termination resistor, if needed, should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS180-03. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.

A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 6 and 3, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.

When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. value of these capacitors is given by the following equation:

Stresses above the ratings listed below can cause permanent damage to the ICS180-03. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V

Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)

 

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