|Description||Clock Synthesizer for Portable Systems|
|Company||Integrated Circuit System|
|Datasheet||Download ICS149317 datasheet
The is a low-power, low-jitter clock synthesizer designed to replace multiple crystals and oscillators in portable audio/video systems. The device generates a 37 MHz processor clock, a 48 MHz USB clock, a fixed 22.5792 MHz audio clock, a selectable 24.576 MHz or 22.5792 MHz audio clock, and a 27MHz reference clock for video. Using ICS' proprietary mix of analog and digital Phase-Locked Loop (PLL) technology, the device spreads the frequency spectrum of the 37 MHz output, reducing the peak amplitude to 16 dB. An output enable (OE) pin lowers the chip power consumption while tri-stating all outputs.Features
Extremely low operating current (11 mA) Packaged in 20-pin QFN (Pb-free) Input crystal or clock frequency of 27 MHz Output reference frequency of 27 MHz Fixed output frequencies of 37 MHz, 48 MHz and 22.5792 MHz Selectable output frequency of either 22.5792 MHz or 24.576 MHz Configurable spread spectrum on 37 MHz output Operating core voltage 1.8 V Output voltage 2.5 V Advanced, low-power CMOS processPLL4 27 MHz clock or crystal input X1 Crystal Oscillator/ Clock Buffer 5 GND
Power Output Power Input Power Output Power Input Power Output Power Output Power Output Connect to ground.
48 MHz clock output. High impedance state when OE=1. Output voltage level. Connect 2.5 V. Same voltage as pin 12. Output Enable pin. See table above. Internal pull-down resistor. Connect V. 22.5792 MHz clock output. Internal pull-down. High impedance state when OE=1. Connect to ground. I2C bus clock pin. Internal pull-up resistor. I2C bus data pin. Internal pull-up resistor. Connect to ground. Selectable output clock of either or 24.576M. See table. Internal pull-down. High impedance state. OE=1. Output voltage level. Connect 2.5 V. Same voltage as pin 3. Spread spectrum 37 MHz clock output. See table. Internal pull-down. High impedance state when OE=1. Connect +1.8 V. Connect to ground. Connect to ground. 27 MHz reference clock output. Internal pull-down. High impedance state when OE=1. 2
Connect to 27 MHz crystal or float for clock input. Crystal connection. Connect to 27 MHz crystal or clock input.
As with any high-performance mixed-signal IC, the ICS1493-17 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between each VDD and the PCB ground plane.
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33 series termination resistor should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS1493-17. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
No external crystal load capacitors are required. To save discrete component cost, the ICS1493-17 integrates on-chip capacitance to support a crystal with CL=10 pF. It is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device.
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