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Details, datasheet, quote on part number:1574
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS1574B
User Programmable Laser Engine Pixel Clock Generator
Description
The ICS1574B is a very high performance monolithic phaselocked loop (PLL) frequency synthesizer designed for laser engine applications. Utilizing ICS's advanced CMOS mixedmode technology, the ICS1574B provides a low cost solution for high-end pixel clock generation for a variety of laser engine product applications. The pixel clock output (PCLK) frequency is derived from the main clock by a programmable resettable divider. Operating frequencies are fully programmable with direct control provided for reference divider, feedback divider and post-scaler.
Features ·
Supports high resolution laser graphics. PLL/VCO frequency re-programmable through serial interface port to 400 MHz; allows less than ±1.5ns pixel clock resolution. Laser pixel clock output is synchronized with conditioned beam detect input Ideal for laser printer, copier and FAX pixel clock applications On-chip PLL with internal loop filter On-chip XTAL oscillator frequency reference Resettable, programmable counter gives glitch-free clock alignment Single 5 volt power supply Low power CMOS technology Compact 16-pin 0.150" skinny SOIC package User re-programmable clock frequency supports zoom and gray scale functions
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Block Diagram
Figure 1
1 574 B 8/31/00
ICS1574B
Pin Configuration
PCLKEN XTAL1 XTAL2 DATCLK VSS VSS PCLK
(Do Not Connect) Reser ved
1 2
16 15
DATA HOLD TEST (Connect to VSS)) VDD VDDO Reserved (Do Not Connect) Reserved (Do Not Connect) Reserved (Do Not Connect)
ICS1574B
2
3 4 5 6 7 8
14 13 12 11 10 9
16-Pin Skinny SOIC Pin Descriptions
PIN NUMBER 7 1 2 3 4 16 15 14 8, 9, 10, 11 13 12 5, 6 P I N NA M E PCLK PCLKEN X TA L 1 X TA L 2 DAT C L K DATA HOLD Te s t R e s e r ve d VDD VDDO VSS DESCRIPTION P i xe l c l o c k o u t p u t . PCLK Enable (Input). Q u a r t z c r y s t a l c o n n e c t i o n 1 / ex t e r n a l r e f e r e n c e f r e q u e n cy i n p u t . Quartz crystal connection 2. Data Clock (Input). S e r i a l R eg i s t e r D a t a ( I n p u t ) . HOLD (Input). Test. (Must be connected to VSS.) R e s e r ve d . ( D o N o t C o n n e c t . ) PLL system power (+5V. See application diagram). Output stage power (+5V). Device ground. (Both pins must be connected.)
ICS1574B
PCLK Programmable Divider
The ICS1574B has a programmable divider (referred to in Figure 1 as the PCLK divider) that is used to generate the PCLK clock frequency for the pixel clock output. The modulus of this divider may be set to 3, 4, 5, 6, 8, 10, 12, 16 or 20 under register control. The design of this divider permits the output duty factor to be 50/50, even when an odd modulus is selected. The input frequency to this divider is the output of the PLL post-scaler described below: The phase of the PCLK output is aligned with the internal high frequency PLL clock (FVCO) immediately after the assertion of the PCLKEN input pulse (active low if PCLKEN_POL bit is 0 or active high if PCLKEN_POL bit is 1). When PCLKEN is deasserted, the PCLK output will complete its current cycle and remain at VDD until the next PCLKEN p u l s e . The minimum time PCLKEN must be disabled (TPULSE) is 1/FPCLK. See Figure 2a for an example of PCLKEN enable (negative polarity) vs. PCLK timing sequences.
TK = K · TVCO
Td = LOGIC PROP.DELAY TIME (typically 9ns with a 10pF load on PCLK) TVCO = 1/FVCO
Figure 2b
The resolution of Ton is one VCO cycle.
The time required for a PCLK cycle start following a PCLKEN enable is described by Figure 2b and the following table:
K Va l u e s P C L K D iv i d e r
3 4a 4b 5 6 8a 8b 10 12 16a 16b 20
K
2 3.5 3 4.5 3.5 5.5 5 7 6.5 9.5 9 12
Figure 2a
Typical values for Tr and Tf with a 10pF load on PCLK are 1ns.
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ICS1574B
PLL Post-Scaler
A programmable post-scaler may be inserted between the VCO and the PCLK divider of the ICS1574B. This is useful in generating lower frequencies, as the VCO has been optimized for high-frequency operation. The post-scaler is not affected by the PCLKEN input. The post-scaler allows the selection of: · VCO frequency · VCO frequency divided by 2 · VCO frequency divided by 4 · AUX-EN Test Mode back divider makes use of a dual-modulus prescaler technique that allows the programmable counters to operate at low speed without sacrificing resolution. This is an improvement over conventional fixed prescaler architectures that typically impose a factor-of-four (or larger) penalty in this respect. Table 1 permits the derivation of "A" & "M" converter programming directly from desired modulus.
Digital Inputs
The programming of the ICS1574B is performed serially by using the DATCLK, DATA, and HOLD pins to load an internal shift register. DATA is shifted into the register on the rising edge of DATCLK. The logic value on the HOLD pin is latched at the same time. When HOLD is low, the shift register may b e loaded without disturbing the operation of the ICS1574B. When high, the shift register outputs are transferred to the control registers, and the new programming i n f o r m a t i o n becomes active. Ordinarily, a high level should be placed on the HOLD pin when the last data bit is presented. See Figure 3 for the programming sequence. The PCLKEN input polarity may be programmed under register control via Bit 39.
P L L Synthesizer Description -- Ratiometric Mode
The ICS1574B generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency provided to the PLL (see Figure 1). The reference frequency is generated by an on-chip crystal oscillator or the reference frequency may be applied to the ICS1574B from an external frequency source. The phase-frequency detector shown in the block diagram drives the voltage-controlled oscillator, or VCO, to a frequency that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. This occurs when:
F(VCO): = F(XTAL1) · Feedback Divider
Reference Divider
This expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers). The VCO gain is programmable, permitting the ICS1574B to be optimized for best performance at all operating frequencies. The reference divider may be programmed for any modulus from 1 to 128 in steps of one. The feedback divider may be programmed for any modulus from 37 through 392 in steps of one. Any even modulus from 392 through 784 can also be achieved by setting the "double" bit which doubles the feedback divider modulus. The feed-
Figure 3 Output Description
T h e PCLK output is a high-current CMOS type drive whose frequency is controlled by a programmable divider that may be selected for a modulus of 3, 4, 5, 6, 8, 10, 12, 16 or 20. It may also be suppressed under register control via Bit 46.
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ICS1574B
Reference Oscillator and Crystal Selection
T h e ICS1574B has circuitry on-board to implement a Pierce oscillator with the addition of only one external component, a quartz crystal. Pierce oscillators operate the crystal in anti- (also called parallel-) resonant mode. See the AC C h a r a c t e r i s t i c s for the effective capacitive loading to specify when ordering crystals. S e r i e s - r e s o n a n t crystals may also be used with the ICS1574B. Be aware that the oscillation frequency will be slightly higher than the frequency that is stamped on the can (typically 0.025 0.05%). As the entire operation of the phase-locked loop depends on having a stable reference frequency, we recommend that the crystal be mounted as closely as possible to the package. Avoid routing digital signals or the ICS1574B outputs underneath or near these traces. It is also desirable to ground the crystal can to the ground plane, if possible. If an external reference frequency source is to be used with the ICS1574B, it is important that it be jitter-free. The rising and falling edges of that signal should be fast and free of noise for best results. The loop phase can be locked to either the rising or falling edges of the XTAL1 input signals, and is controlled by Bit 56.
Programming Notes
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VCO Frequency Range: Use the post-divider to keep the VCO frequency as high as possible within its operating range. D i v i d e r Range: For best results in normal situations keep the reference divider modulus as short as possible (for a frequency at the output of the reference divider in t h e few hundred kHz to several MHz range). If you need to go to a lower phase comparator reference freq u e n c y (usually required for increased frequency accuracy), that is acceptable, but jitter performance will suffer somewhat. VCO Gain Programming: Use the minimum gain which c a n reliably achieve the VCO frequency desired, as shown here:
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VCO GAI N 4 5 6 7
MA X F R E QU E N C Y 100 MHz 200 MHz 300 MHz 400 MHz
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Power-On Initialization
The ICS1574B has an internal power-on reset circuit that performs the following functions: 1 ) Selects the modulus of the PCLK divider to be four (4). 2 ) Sets the multiplexer to pass the reference frequency to PCLK divider input. These functions should allow initialization for most applic a t i o n s that cannot immediately provide for register programming upon system power-up. Because the power-on reset circuit is on the VDD supply, and because that supply is filtered, care must be taken to allow the reset to de-assert before programming. A safe guideline is to allow 20 microseconds after the VDD supply reaches 4 volts.
Phase Detector Gain: For most applications and divider ranges, set P [1, 0 ] = 10 and set P[2] = 1. Under some c i r c u m s t a n c e s , setting the P [ 2 ] bit "on" can reduce jitter. During operation at exact multiples of the crystal frequency, P[2] bit = 0 may provide the best jitter performance.
Board Test Support
It is often desirable to statically control the levels of the output pins for circuit board test. The ICS1574B supports t h i s through a register programmable mode, AUX-EN. When this mode is set, a register bit directly controls the logic level of the PCLK pin. This mode is activated when the S[0] and S[1] bits are both set to logic 1. See Register Mapping for details.
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