Details, datasheet, quote on part number: HY5DU12822ALT_D
PartHY5DU12822ALT_D
CategoryMemory => DRAM => DDR SDRAM => 512 Mb
Description
CompanyHynix Semiconductor
DatasheetDownload HY5DU12822ALT_D datasheet
  

 

Features, Applications

This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 2003 1

The HY5DU12422A(L)T, HY5DU12822A(L)T and HY5DU121622A(L)T are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.

FEATURES

VDD, VDDQ 2.5V 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable /CAS latency supported Programmable burst length with both sequential and interleave mode Internal four bank operations with single pulsed /RAS Auto refresh and self refresh supported tRAS lock out function supported 8192 refresh cycles / 64ms JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Full and Half strength driver option controlled by EMRS


 

Some Part number from the same manufacture Hynix Semiconductor
HY5DU12822AT
HY5DU12822AT_D
HY5DU12822LT 512M(64Mx8) DDR Sdram
HY5DU12822T
HY5DU281622ALT 128M(8Mx16) DDR Sdram
HY5DU281622ALT
HY5DU281622AT 128M(8Mx16) DDR Sdram
HY5DU281622AT-6
HY5DU281622AT-H
HY5DU281622AT-X
HY5DU281622DLT
HY5DU281622DLT 128M(8Mx16) DDR Sdram
HY5DU281622DLT-X
HY5DU281622DT 128M(8Mx16) DDR Sdram
HY5DU281622DT-6
HY5DU281622LT-X
HY5DU281622T-H
HY5DU281622T-X
HY5DU283222AF
HY5DU283222AF-2
HY5DU283222AF-33

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