Details, datasheet, quote on part number: HY5DU121622T-L
PartHY5DU121622T-L
CategoryMemory => DRAM => DDR SDRAM => 512 Mb
Description512M(32Mx16) DDR Sdram
CompanyHynix Semiconductor
DatasheetDownload HY5DU121622T-L datasheet
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Features, Applications

This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 02 1

1. Rev 0.2 (Jul. 01) 1) Preliminary IDD Specification defined 2. Rev 0.3 (Feb. 02) 1) tHZ/tLZ Specification defined 2) IDD4W Specification changed from 200mA 3) tIS/tIH at DDR200 changed from 1.1ns 3. Rev 0.4 (Feb. 02) 1) tCK max DDR2666A/B, DDR2000 changed 12ns 2) tWR SPEC. at DDR200 changed 3) IDD0 SPEC. changed from at DDR266A/B and DDR200 4) tQHS at DDR200 changed from 0.75ns 4. Rev 0.5 (May. 02) 1) IDD SPEC. updated 2) Input leakage current changed from +/-2uA 5. Rev 0.6 (May. 02) 1) IDD SPEC.(IDD2Q, IDD7A) updated

DESCRIPTION

The Hynix HY5DU12422(L)T, HY5DU12822(L)T and HY5DU121622(L)T are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.

FEATURES

VDD, VDDQ 2.5V 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable /CAS latency supported Programmable burst length with both sequential and interleave mode Internal four bank operations with single pulsed /RAS Auto refresh and self refresh supported tRAS lock out function supported 8192 refresh cycles / 64ms JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Full and Half strength driver option controlled by EMRS

Standard Low Power Standard Low Power Standard Low Power
* X means speed grade JEDEC specification compliant

 

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