Details, datasheet, quote on part number: HY57V64820HGT
PartHY57V64820HGT
CategoryMemory => DRAM => SDR SDRAM => 64 Mb
Description
CompanyHynix Semiconductor
DatasheetDownload HY57V64820HGT datasheet
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Features, Applications
DESCRIPTION

The Hynix a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V64820HG is organized HY57V64820HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted a `2N` rule.)

FEATURES

Single 3.30.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type or Full page for Sequential Burst or 8 for Interleave Burst Programmable CAS Latency 2, 3 Clocks

This document is a general product description and is subject to change without notice.Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 02 1

VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC /WE /CAS /RAS /CS A2 A3 VDD VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE A5 A4 VSS

PIN CLK CKE ~ A11 Clock Enable Chip Select Bank Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address ~ RA11, Column Address ~ CA8 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection

2Mx8 Bank3 Row Pre Decoders 2Mx8 Bank 2 X decoders 2Mx8 Bank 1 X decoders 2Mx8 Bank 0 X decoders DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate


 

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