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Details, datasheet, quote on part number:M34519M6
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Datasheet text preview:
4519 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0007-0200Z Rev.2.00 2003.04.15
DESCRIPTION
The 4519 Group is a 4-bit single-chip microcomputer designed with C M O S technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has one or two reload register), a 10-bit A-D converter, interrupts, and oscillation circuit switch function. The various microcomputers in the 4519 Group include variations of the built-in memory size as shown in the table below.
FEATURES
Minimum instruction execution time .......... 0.5 µs (at 6 MHz oscillation frequency, in XIN through-mode) Supply voltage Mask ROM version ...... 1.8 to 5.5 V One Time PROM version ............ 2.5 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode) Timers Timer 1 ..... 8-bit timer with a reload register Timer 2 ..... 8-bit timer with a reload register Timer 3 ..... 8-bit timer with a reload register Timer 3 ......... 8-bit timer with two reload registers Product M34519M6-XXXFP M34519M8-XXXFP M34519E8FP (Note)
Note: Shipped in blank.
Interrupt ...... 8 sources Key-on wakeup function pins ......... 10 Serial I/O ..... 8 bits 1 A-D converter ...... 10-bit successive approximation method, 8ch Voltage drop detection circuit Reset occurrence ... Typ. 3.5 V (Ta = 25 °C) Reset release ......... Typ. 3.7 V (Ta = 25 °C) Watchdog timer Clock generating circuit (ceramic resonator/RC oscillation/quartz-crystal oscillation/internal ring oscillator) LED drive directly enabled (port D)
APPLICATION
Electrical household appliance, consumer electronic products, office automation equipment, etc.
ROM (PROM) size ( 10 bits) 6144 words 8192 words 8192 words
RAM size ( 4 bits) 384 words 384 words 384 words
Package 42P2R-A 42P2R-A 42P2R-A
ROM type Mask ROM Mask ROM One Time PROM
Rev.2.00
2003.04.15
page 1 of 159
PRELIMINARY
4519 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
PIN CONFIGURATION
P13 D0 D1 D2 D3 D4 D5 D6/CNTR0 D7/CNTR1 P50 P51 P52 P53 P20/SCK P21/SOUT P22/SIN RESET CNVSS XOUT XIN VSS
1 2 3 4 5 6
42 41 40 39 38 37
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P12 P11 P10 P03 P02 P01 P00 P43/AIN7 P42/AIN6 P41/AIN5 P40/AIN4 P63/AIN3 P62/AIN2 P61/AIN1 P60/AIN0 P33 P32 P31/INT1 P30/INT0 VDCE VDD
OUTLINE 42P2R-A
M34519Mx-XXXFP M34519E8FP
Pin configuration (top view) (4519 Group)
Rev.2.00
2003.04.15 page 2 of 159
Block diagram (4519 Group)
Rev.2.00
4 4 3 4 4 4 4 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 System clock generation circuit XIN -XOUT (Ceramic/Quartz-crystal/RC) Built-in ring oscillator Voltage drop detection circuit
4519 Group
I/O port
Port P0
Internal peripheral functions
2003.04.15 page 3 of 159
Timer
Timer 1(8 bits) Timer 2(8 bits) Timer 3(8 bits) Timer 4(8 bits)
Watchdog timer (16 bits)
A-D converter (10 bits 8 ch)
Memory
ROM
6144, 8192 words 10 bits
Serial I/O (8 bits 1)
4500 series CPU core
ALU(4 bits)
Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level)
RAM
384 words 4 bits
Port D
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
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