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Details, datasheet, quote on part number:M34518M8
 
 
Part:M34518M8
Category:Microprocessors => 4 bit => 4500 series
Description:
Company:Renesas
Datasheet:Download M34518M8 datasheet   File size : 1556 kB
Request For quote:  Find where to buy M34518M8
 



Datasheet text preview:
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
4518 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0008-0200Z Rev.2.00 2003.04.15
DESCRIPTION
The 4518 Group is a 4-bit single-chip microcomputer designed with C M O S technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has one or two reload register), a 10-bit A-D converter, interrupts, and oscillation circuit switch function. The various microcomputers in the 4518 Group include variations of the built-in memory size as shown in the table below.
FEATURES
q Minimum instruction execution time .......... 0.5 µs (at 6 MHz oscillation frequency, in XIN through-mode) q Supply voltage Mask ROM version ...... 1.8 to 5.5 V One Time PROM version ............ 2.5 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode) q Timers Timer 1 ..... 8-bit timer with a reload register Timer 2 ..... 8-bit timer with a reload register Timer 3 ..... 8-bit timer with a reload register Timer 3 ......... 8-bit timer with two reload registers Product M34518M2-XXXFP M34518M2-XXXSP M34518M4-XXXFP M34518M4-XXXSP M34518M6-XXXFP M34518M8-XXXFP M34518E8FP (Note) M34518E8SP (Note)
Note: Shipped in blank.
q Interrupt ...... 8 sources q Key-on wakeup function pins ......... 10 q Serial I/O ..... 8 bits 1 q A-D converter ...... 10-bit successive approximation method, 4ch q Voltage drop detection circuit Reset occurrence ... Typ. 3.5 V (Ta = 25 °C) Reset release ......... Typ. 3.7 V (Ta = 25 °C) q Watchdog timer q Clock generating circuit (ceramic resonator/RC oscillation/quartz-crystal oscillation/internal ring oscillator) q LED drive directly enabled (port D)
APPLICATION
Electrical household appliance, consumer electronic products, office automation equipment, etc.
ROM (PROM) size ( 10 bits) 2048 words 2048 words 4096 words 4096 words 6144 words 8192 words 8192 words 8192 words
RAM size ( 4 bits) 256 words 256 words 256 words 256 words 384 words 384 words 384 words 384 words
Package 32P6U-A 32P4B 32P6U-A 32P4B 32P6U-A 32P6U-A 32P6U-A 32P4B
ROM type Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One Time PROM One Time PROM
Rev.2.00
2003.04.15
page 1 of 156
PRELIMINARY
4518 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
PIN CONFIGURATION
P31/INT1
17 16 15 14
P63/AIN3
P62/AIN2
P61/AIN1
19
24
23
22
21
20
18
P03 P10 P11 P12 P13 D0 D1 D2
P60/AIN0
P 02
P 01
P 00
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
P30/INT0 VDCE VDD VSS XIN XOUT CNVSS RESET
M34518Mx-XXXFP M34518E8FP
13 12 11 10 9
D6/CNTR0
D7/CNTR1
OUTLINE 32P6U-A
Pin configuration (top view) (4518 Group)
D0 D1 D2 D3 D4 D5 D6/CNTR0 D7/CNTR1 P20/SCK P21/SOUT P22/SIN RESET CNVSS XOUT XIN VSS
P21/SOUT
P20/SCK
P22/SIN
D3
D4
D5
1 2 3 4 5
32 31 30 29 28
P13 P12 P11 P10 P03 P02 P01 P00 P63/AIN3 P62/AIN2 P61/AIN1 P60/AIN0 P31/INT1 P30/INT0 VDCE VDD
M34518Mx-XXXSP M34518E8SP
6 7 8 9 10 11 12 13 14 15 16
27 26 25 24 23 22 21 20 19 18 17
OUTLINE 32P4B
Pin configuration (top view) (4518 Group)
Rev.2.00
2003.04.15 page 2 of 156
Block diagram (4518 Group)
Rev.2.00
4 4 3 2 4 Port P0 Port P1 Port P2 Port P3 Port P6 System clock generation circuit XIN -XOUT (Ceramic/Quartz-crystal/RC) Built-in ring oscillator Voltage drop detection circuit
4518 Group
I/O port
Internal peripheral functions
2003.04.15 page 3 of 156
Timer
Timer 1(8 bits) Timer 2(8 bits) Timer 3(8 bits) Timer 4(8 bits)
Watchdog timer (16 bits)
A-D converter (10 bits 4 ch)
Memory
ROM
2048, 4096, 6144, 8192 words 10 bits
Serial I/O (8 bits 1)
4500 series CPU core
ALU(4 bits)
Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level)
RAM
256, 384 words 4 bits
Port D
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
8