Details, datasheet, quote on part number: GS8322ZV72C-200
PartGS8322ZV72C-200
CategoryMemory => Memory Chips => 6329952
Title512K X 72 ZBT SRAM, 6.5 ns, PBGA209
Description
CompanyGSI Technology
DatasheetDownload GS8322ZV72C-200 datasheet
Specifications 
Memory CategorySRAM Chip
Density37749 kbits
Number of Words512 k
Bits per Word72 bits
Package TypeBGA, 14 X 22 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-209
Pins209
Logic FamilyCMOS
Supply Voltage2.5V
Access Time6.5 ns
Operating Temperature0 to 70 C (32 to 158 F)

 

Features, Applications

NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs V +10%/10% core power supply 3.3 V I/O supply User-configurable Pipeline and Flow Through mode ZQ mode pin for user-selectable high/low output drive IEEE 1149.1 JTAG-compatible Boundary Scan LBO pin for Linear or Interleave Burst mode Pin-compatible with 4Mb, 8Mb, and 16Mb devices Byte write operation (9-bit Bytes) 3 chip enable signals for easy depth expansion ZZ Pin for automatic power-down JEDEC-standard or 209-Bump BGA package Pb-Free packages available

Because is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8322Z18/36/72 may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8322Z18/36/72 is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard or 209-bump BGA package.

The a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

DQG DQPG DQC NC DQH DQPD DQD 2 DQG DQPC DQC NC DQH DQPH DQD BC BH VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A TDI A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A 6 ADV E1 G VDD ZQ MCH MCL MCH CKE FT MCL MCH ZZ VDD LBO A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD BE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A TDO BF BA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQB DQPF DQF NC DQA DQPA DQE 11 DQB DQPB DQF NC DQA DQPE DQE

Description
Address field LSBs and Address Counter Preset Inputs Address Inputs

Byte Write Enable for DQA, DQB I/Os; active low Byte Write Enable for DQC, DQD I/Os; active low Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Chip Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Must Connect High Must Connect High Must Connect Low Write Enable; active low FLXDrive Output Impedance Control Low = Low Impedance [High Drive], High = High Impedance [Low Drive] Clock Enable; active low


 

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