Details, datasheet, quote on part number: GS8322Z18C-250I
PartGS8322Z18C-250I
CategoryMemory => Memory Chips => 6329049
Title2M X 18 ZBT SRAM, 7.5 ns, PBGA119
Description
CompanyGSI Technology
DatasheetDownload GS8322Z18C-250I datasheet
Specifications 
Memory CategorySRAM Chip
Density37749 kbits
Number of Words2000 k
Bits per Word18 bits
Package Type14 X 22 MM, 1.27 MM PITCH, FPBGA-119
Pins119
Logic FamilyCMOS
Supply Voltage2.5V
Access Time7.5 ns
Operating Temperature0 to 70 C (32 to 158 F)

 

Features, Applications

NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs V +10%/10% core power supply 3.3 V I/O supply User-configurable Pipeline and Flow Through mode ZQ mode pin for user-selectable high/low output drive IEEE 1149.1 JTAG-compatible Boundary Scan LBO pin for Linear or Interleave Burst mode Pin-compatible with 4Mb, 8Mb, and 16Mb devices Byte write operation (9-bit Bytes) 3 chip enable signals for easy depth expansion ZZ Pin for automatic power-down JEDEC-standard 119-bump and 165-bump BGA packages RoHS-compliant packages available

Because is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8322Z18/36A may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8322Z18/36A is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard or 165-bump BGA package.

The a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Rev: GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

VDDQ NC DQC VDDQ DQC VDDQ DQD VDDQ DQD NC VDDQ E2 A DQPC DQC VDD DQD DQPD A NC TMS VSS BC VSS NC VSS BD VSS LBO A TDI 4 A ADV VDD A W VDD CK NC CKE A1 A0 VDD A TCK VSS BB VSS NC VSS BA VSS FT A TDO E3 A DQPB DQB VDD DQA DQPA NC 7 VDDQ NC DQB VDDQ DQB VDDQ DQA VDDQ DQA NC ZZ VDDQ

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

VDDQ NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC VDDQ A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A TMS VSS BB VSS NC VSS NC VSS LBO A TDI 4 A ADV VDD A W VDD CK NC CKE A1 A0 VDD A TCK VSS NC VSS NC VSS BA VSS FT A TDO E3 A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC 7 VDDQ NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ


 

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