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Part: 74VHC4046MTCX
Category:
Description: CMOS Phase Lock Loop
Company: Fairchild Semiconductor
Datasheet: Download 74VHC4046MTCX datasheet File size : 110 kB
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Datasheet text preview:
74VHC4046 CMOS Phase Lock Loop
April 1994 Revised April 1999
74VHC4046 CMOS Phase Lock Loop
General Description
The VHC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and VCO sections. This device contains a low power linear voltage controlled oscillator (VCO), a source follower, and three phase comparators. The three phase comparators have a common signal input and a common comparator input. The signal input has a self biasing amplifier allowing signals to be either capacitively coupled to the phase comparators with a small signal or directly coupled with standard input logic levels. This device is similar to the CD4046 except that the Zener diode of the metal gate CMOS device has been replaced with a third phase comparator. Phase Comparator I is an exclusive OR (XOR) gate. It provides a digital error signal that maintains a 90 phase shift between the VCO's center frequency and the input signal (50% duty cycle input waveforms). This phase detector is more susceptible to locking onto harmonics of the input frequency than phase comparator I, but provides better noise rejection. Phase comparator III is an SR flip-flop gate. It can be used to provide the phase comparator functions and is similar to the first comparator in performance. Phase comparator II is an edge sensitive digital sequential network. Two signal outputs are provided, a comparator output and a phase pulse output. The comparator output is a 3-STATE output that provides a signal that locks the VCO output signal to the input signal with 0 phase shift between them. This comparator is more susceptible to noise throwing the loop out of lock, but is less likely to lock onto harmonics than the other two comparators. In a typical application any one of the three comparators feed an external filter network which in turn feeds the VCO input. This input is a very high impedance CMOS input which also drives the source follower. The VCO's operating frequency is set by three external components connected to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided to disable the VCO and the source follower, providing a method of putting the IC in a low power state. The source follower is a MOS transistor whose gate is connected to the VCO input and whose drain connects the Demodulator output. This output normally is used by tying a resistor from pin 10 to ground, and provides a means of looking at the VCO input without loading down modifying the characteristics of the PLL filter.
Features
s Low dynamic power consumption: s Maximum VCO operating frequency: (VCC = 4.5V) Comparator I: Comparator II: Comparator III: 25 ns 30 ns 25 ns (VCC = 4.5V) 12 MHz
s Fast comparator response time (VCC = 4.5V)
s VCO has high linearity and high temperature stability s Pin and function compatible with the 74HC4046
Ordering Code:
Order Number 74VHC4046M 74VHC4046MTC 74VHC4046N Package Number M16A MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
© 1999 Fairchild Semiconductor Corporation
DS011675.prf
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74VHC4046
Connection Diagram
Block Diagram
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74VHC4046
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C (Note 4)
Conditions
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V -40 +85 1000 500 400 °C ns ns ns 2 0 Max 6 VC C Units V V
-0.5 to + 7.0V -1.5 to VCC +1.5V -0.5 to VCC + 0.5V ±20 mA ±25 mA ±50 mA -65°C +150°C 600 mW 500 mW
Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage
V CC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V
TA=25°C Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4 .5 6.0 4.2 5.7 0 0 0 0.2 0.2 20 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 50 ±0.25 30 600 40 750
TA=-40 to 85°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 80 ±2.5 65 1200
Units V V V V V V V V V V V V V V V V µA µA µA µA µA
VIN = VIH or VIL |IOUT| 20 µA VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA
2.0V 4.5V 6.0V 4.5V 6.0V 2.0V 4.5V 6.0V
VOL
Maximum LOW Level Output Voltage
VIN = VIH or VIL |IOUT| 20 µA VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA
4.5V 6.0V 6.0V 6.0V 6.0V 6.0V 6.0V
IIN IIN IOZ ICC
Maximum Input Current (Pins 3,5,9) VIN = VCC or GND Maximum Input Current (Pin 14) Maximum 3-STATE Output Leakage Current (Pin 13) Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 µA VIN = V CC or GND Pin 14 Open VIN = VCC or GND VOUT = VCC or GND
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for VHC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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74VHC4046
AC Electrical Characteristics
VCC = 2.0 to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified.) Symbol Parameters AC Coupled Input Sensitivity, Signal In tr, tf Maximum Output Rise and Fall Time CIN Maximum Input Capacitance Phase Comparator I tPHL, tPLH Maximum Propagation Delay Phase Comparator II tPZL Maximum 3-STATE Enable Time tPZH, tPHZ Maximum 3-STATE Enable Time tPLZ Maximum 3-STATE Disable Time tPHL, tPLH Maximum Propagation Delay HIGH-to-LOW to Phase Pulses Phase Comparator III tPHL, tPLH Maximum Propagation Delay CPD Maximum Power Dissipation Capacitance Voltage Controlled Oscillator (Specified to operate from VCC = 3.0V to 6.0V) fMAX Maximum Operating Frequency C1 = 50 pF R1 = 100 R2 = VCOin = VCC C1 = 0 pF R1 = 100 VCOin = VCC Duty Cycle Demodulator Output Offset Voltage VCOin Vdem Offset Variation Rs = 20 k VCOin = 1.75V 2.25V 2.75V 4.5V 0.65 0.1 0.75 V Rs = 20 k 4.5V 0.75 1.3 1 .5 V 50 % 4.5V 6.0 12 14 MHz MHz 4.5V 6.0V 7 11 4 .5 7 MHz MHz All Comparators VIN = V CC and GND 3.3V 4.5V 6.0V 75 25 22 130 117 40 34 146 50 43 ns ns ns pF 3.3V 4.5V 6.0V 3.3V 4.5V 6.0V 3.3V 4.5V 6.0V 3.3V 4.5V 6.0V 75 25 22 88 30 25 90 32 28 100 34 27 130 45 38 140 48 41 140 48 41 146 50 43 160 56 48 175 60 51 175 60 51 180 63 53 ns ns ns ns ns ns ns ns ns ns ns ns 3.3V 4.5V 6.0V 65 25 20 117 40 34 146 50 43 ns ns ns Conditions C (series) = 100 pF fIN = 500 kHz VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 7 TA=25C Typ 25 50 135 30 9 8 100 150 250 75 15 12 TA=-40 to 85°C Guaranteed Limits 150 200 300 95 19 15 Units mV mV mV ns ns ns pF
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74VHC4046
Typical Performance Characteristics
Typical Center Frequency vs R1, C1 VCC = 4.5V Typical Center Frequency vs R1, C1 VCC = 6V
Typical Offset Frequency vs R2, C1 VCC = 4.5V
Typical Offset Frequency vs R2, C1 VCC = 6V
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