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Part: 74ACT18823MTD
Category:
Description: 18-Bit D-type Flip-flop With 3-STATE Outputs
Company: Fairchild Semiconductor
Datasheet: Download 74ACT18823MTD datasheet File size : 232 kB
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74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
August 1999 Revised October 1999
74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACT18823 contains eighteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP), Clear (CLR), Clock Enable (EN) and Output Enable (OE) are common to each byte and can be shorted together for full 18-bit operation.
Features
s Broadside pinout allows for easy board layout s Separate control logic for each byte s Extra data width for wider address/data paths or buses carrying parity s Outputs source/sink 24 mA s TTL-compatible inputs
Ordering Code:
Order Number 74ACT18823SSC 74ACT18823MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OEn CLRn E Nn CP n I0I17 O0O17 Description Output Enable Input (Active LOW) Clear (Active LOW) Clock Enable (Active LOW) Clock Pulse Input Inputs Outputs
FACTTM is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500294
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74ACT18823
Functional Description
The ACT18823 consists of eighteen D-type edge-triggered flip-flops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. The buffered clock (CPn) and buffered Output Enable (OEn) are common to all flip-flops within that byte. The flip-flops will store the state of their individual D inputs that meet set-up and hold time requirements on the LOW-to-HIGH CPn transition. With OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the impedance state. Operation of the OEn input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear (CLRn) and Clock Enable (ENn) pins. These devices are ideal for parity bus interfacing in high performance systems. When CLRn is LOW and OEn is LOW, the outputs are LOW. When CLRn is HIGH, data can be entered into the flip-flops. When ENn is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the ENn is HIGH, the outputs do not change state, regardless of the data or clock input transitions.
Function Table
(Note 1) Inputs OE CLR H H H L H L H H L L X X L L H H H H H H EN L L X X H H L L L L CP Internal Output
X X X
In L H X X X X L H L H
Q L H L L NC NC L H L H
On Z Z Z L Z NC Z Z L H
Function High Z High Z Clear Clear Hold Hold Load Load Load Load
H= HIGH Voltage Level L= LOW Voltage Level X= Immaterial Z= High Impedance = LOW-to-HIGH Transition NC= No Change
X
Note 1: The table represents the logic for one byte. The two bytes are independent of each other and function identically.
Logic Diagrams
Byte 1 (0:8)
Byte 2 (9:17)
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74ACT18823
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC +0.5V DC Output Diode Current (IOK) VO = -0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current Per Output Pin Junction Temperature PDIP/SOIC Storage Temperature +140°C -65°C to +150°C ± 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V ± 50 mA -20 mA +20 mA -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40°C to +85°C 125 mV/ns
DC Electrical Characteristics
Symbol VIH VIL VOH Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage Parameter VCC (V) 4.5 5 .5 4.5 5 .5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4 .5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Maximum Quiescent Supply Current Minimum Dynamic Output Current (Note 4) 5.5 5.5 5 .5 5.5 5.5 0.6 8 .0 0.001 0.001 TA = +25°C Typ 1 .5 1.5 1.5 1.5 4.49 5.49 2.0 2 .0 0.8 0 .8 4 .4 5 .4 3 .86 4 .86 0.1 0.1 0 .36 0 .36 ± 0.5 ± 0.1 TA = -40°C to +85°C Guaranteed Limits 2 .0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0 .1 0 .1 0.44 0.44 ±5.0 ±1.0 1 .5 80.0 75 -75 µA µA mA µA mA mA V Units V V V Conditions VOUT = 0.1V or VCC -0.1V VOUT = 0.1V or VCC -0.1V IOUT = -50 µA VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 3) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 3) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC -2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min
Note 3: All outputs loaded; thresholds associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
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74ACT18823
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 5) fMAX Maximum Clock 5.0 Frequency tPHL tPLH tPHL Propagation Delay 5.0 CPn to On Propagation Delay 5.0 CLRn to On tPZL tPZH tPLZ tPHZ
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.
TA = +25°C CL = 50 pF Min 100 2.0 2.0 2 .0 2.0 9 .0 9 .0 9.0 9 .0 9 .0 7 .0 8 .0 Max
TA = -40°C to +85°C CL = 50 pF Min 90 2.0 2.0 2 .0 2.0 2.0 1.5 1.5 9 .5 ns 9 .5 9.5 10.0 ns 10.0 7 .5 ns 8 .5 ns Max MHz Units
Output Enable Time 5.0
2.0 Output Disable Time 5.0 1.5 1.5
AC Operating Requirements
VCC Symbol Parameter (V) (Note 6) tS Setup Time, HIGH or LOW, 5.0 Input to Clock tH Hold Time, HIGH or LOW, 5.0 Input to Clock tS Setup Time, HIGH or LOW, 5.0 Enable to Clock tH Hold Time, HIGH or LOW, 5.0 Enable to Clock tW CPn Pulse Width, HIGH or LOW tW CLRn Pulse Width, HIGH or LOW trec Recovery Time, 5.0 CLRn to CPn
Note 6: Voltage Range 5.0 is 5.0V ± 0.5V.
TA = +25°C CL = 50 pF
TA = -40°C to +85°C CL = 50 pF Units
Guaranteed Minimum 3.0 3.0 ns
1.5
1.5
ns
3.0
3.0
ns
1.5
1.5
ns
5.0
4.0
4.0
ns
5.0
4.0
4.0
ns
6.0
6.0
ns
Capacitance
Symbol CIN CPD Parameter Input Pin Capacitance Power Dissipation Capacitance Typ 4.5 95 Units pF pF VCC = 5.0V VCC = 5.0V Conditions
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74ACT18823
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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