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Part: 74ABT16500C
Category:
Logic
-> Bus Interface
-> Bus Oriented Circuits
Description: 18-Bit Registered Bus Transceiver With 3-STATE Outputs
Company: Fairchild Semiconductor
Datasheet: Download 74ABT16500C datasheet File size : 294 kB
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Datasheet text preview:
74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs
April 1993 Revised January 1999
74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs
General Description
The ABT16500 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. Output-enable OEAB is active-high. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active LOW). To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Features
s Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode s Flow-through architecture optimizes PCB layout s Guaranteed latch-up protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability
Ordering Code:
Order Number 74ABT16500CSSC 74ABT16500CMTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the letter suffix "X" to the ordering code.
Connection Diagram
Pin Assignment for SSOP
Function Table
OEAB L H H H H H H L E AB X H H L L L L
(Note 1) Output A X L H L H X X B Z L H L H B0 (Note 2) B0 (Note 3)
Inputs CLKAB X X X H L
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 2: Output level before the indicated steady-state input conditions were established. Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW.
© 1999 Fairchild Semiconductor Corporation
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74ABT16500
Logic Diagram
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74ABT16500
Absolute Maximum Ratings(Note 4)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 5) Input Current (Note 5) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to 5.5V -0.5V to VCC -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA -65°C to +150°C -55°C to +125°C -55°C to +150°C
DC Latchup Source Current Over Voltage Latchup (I/O)
-500 mA 10V
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input 50 mV/ns 20 mV/ns -40°C to +85°C +4.5V to +5.5V
Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 5: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL V CD VOH VOL IIH IB V I IIL VID IIH + IOZH IIL + IOZL IOS IC E X IZ Z ICCH ICCL ICCZ ICCT ICCD Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current -100 -275 50 100 1.0 68 1.0 2.5 No Load 0.23 mA µA µA mA µA mA mA mA/ MHz Max Max 0 .0 Max Max Max Max Max VOUT = 0V VOUT = VCC VOUT = 5.5V; All Others GND All Outputs HIGH An or Bn Outputs Low OEn = VCC, All Others at VCC or GND Additional ICC/Input Dynamic ICC (Note 6)
Note 6: Guaranteed, but not tested.
Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current
M in 2.0
Typ
Max
Units V
VCC
Conditions Recognized HIGH Signal Recognized LOW Signal
0.8 -1.2 2.5 2.0 0.55 1 1 7 -1 -1 4.75 10 -10
V V V V V µA µA µA V µA µA Min Min Min Min Max Max Max 0 .0
IIN = -18 mA IOH = -3 mA IOH = -32 mA IOL = 64 mA VIN = 2.7V (Note 6) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 6) VIN = 0.0V IID = 1.9 µA All Other Pins Grounded
0 - 5.5V VOUT = 2.7V; OE, OE = 2.0V 0 - 5.5V VOUT = 0.5V; OE, OE = 2.0V
Output Leakage Current
VI = VCC - 2.1V All Others at VCC or GND Outputs Open Transparent Mode One Bit Toggling, 50% Duty Cycle
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74ABT16500
DC Electrical Characteristics
Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage -1.5 2.5 2.2 M in Typ 0.7 -1.0 3.0 1.8 1.2 0.8 Max 1.2 Units V V V V V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL = 50 pF; RL = 500 TA = 25°C (Note 7) TA = 25°C (Note 7) TA = 25°C (Note 8) TA = 25°C (Note 9) TA = 25°C (Note 9)
Note 7: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 8: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 9: Max number of data inputs (n) switching. n - 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested.
AC Electrical Characteristics
TA = +25°C Symbol Parameter Min fmax tPLH tP H L tPLH tP H L tPLH tP H L tPZH tPZL tP H Z tPLZ Maximum Clock Frequency Propagation Delay A or B to B or A Propagation Delay LEAB or LEBA to B or A Propagation Delay CLKAB or CLKBA to B or A Propagation Delay OEAB or OEBA to B or A Propagation Delay OEAB or OEBA to B or A 150 1 .5 1 .5 1 .5 1 .5 1 .5 1.5 1 .5 1.5 1 .5 1.5 VCC = +5V CL = 50 pF Typ 200 2.7 3.2 3.1 3.6 3.4 3 .7 2.7 3 .0 3.7 3 .2 4.6 4.6 5.0 5.0 5.3 5.3 5.6 5.6 6.0 6.0 Max TA = -40°C to +85°C VCC = 4.5V5.5V CL = 50 pF M in 150 1.5 1.5 1.5 1.5 1.5 1 .5 1.5 1 .5 1.5 1 .5 4 .6 4 .6 5 .0 5 .0 5 .3 5.3 5 .6 5.6 6 .0 6.0 ns ns ns ns Max MHz ns Units
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74ABT16500
AC Operating Requirements
TA = +25°C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(H) tW(L) Setup Time, A to CLKAB Hold Time, A to CLKAB Setup Time, B to CLKBA Hold Time, B to CLKBA Setup Time, A to LEAB or B to LEBA, CLK HIGH Hold Time, A to LEAB or B to LEBA, CLK HIGH Setup Time, A to LEAB or B to LEBA, CLK LOW Hold Time, A to LEAB or B to LEBA, CLK LOW Pulse Width, LEAB or LEBA, HIGH Pulse Width, CLKAB or CLKBA, HIGH or LOW 4.5 4.5 0 0 4.0 4.0 0 0 1.5 1.5 1.5 1.5 4.5 4.5 1.5 1.5 3.3 3 .3 3.3 3.3 VCC = +5V CL = 50 pF Max Min 4.5 4 .5 0 0 4.0 4 .0 0 0 1.5 1 .5 1.5 1 .5 4.5 4 .5 1.5 1 .5 3 .3 3 .3 3 .3 3 .3 ns ns ns ns ns ns ns ns ns TA = -40°C to +85°C VCC = 4.5V5.5V CL = 50 pF M ax ns Units
Extended AC Electrical Characteristics
TA = -40°C to +85°C VCC = 4.5V5.5V Symbol Parameter CL = 50 pF 18 Outputs Switching (Note 10) Min tPLH tP H L tPLH tP H L tPLH tP H L tPZH tPZL tP H Z tPLZ Output Disable Time Propagation Delay Data to Outputs Propagation Delay LEAB or LEBA to B or A Propagation Delay CLKAB or CLKBA to B or A Output Enable Time 1 .5 1 .5 1 .5 1 .5 1 .5 1.5 1.5 1.5 1 .5 1 .5 Typ M ax 6.5 6.5 6.0 6.0 6.2 6 .2 6 .5 6 .5 6.5 6 .5 2 .0 2 .0 2 .0 2 .0 2 .0 2.0 2.0 2.5 (Note 13) TA = -40°C to +85°C VCC = 4.5V5.5V CL = 250 pF 1 Output Switching (Note 11) Min Max 7.0 7.0 7.5 7.5 7.7 7.7 7.0 7.0 2 .5 2 .5 2 .5 2 .5 2 .5 2.5 2.5 2.5 (Note 13) TA = -40°C to +85°C VCC = 4.5V5.5V CL = 250 pF 18 Outputs Switching (Note 12) M in M ax 9.9 9.2 8.5 8.5 8.5 8 .5 8 .5 8 .5 ns ns ns ns ns Units
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 11: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 12: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: 3-STATE delays are dominated by the RC network (500, 250 pF) on the output and have been excluded from the datasheet.
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