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Details, datasheet, quote on part number:100310
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| Part: | 100310 |
| Category: | Timing Circuits => Clock Distribution => General Purpose/ |
| Description: | Low Skew 2:8 Differential Clock Driver |
| Company: | Fairchild Semiconductor |
| Datasheet: | Download 100310 datasheet File size : 65 kB |
| Request For quote: | Find where to buy 100310
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Datasheet text preview:
100310 Low Skew 2:8 Differential Clock Driver
October 1991 Revised November 1999
100310 Low Skew 2:8 Differential Clock Driver
General Description
The 100310 is a low skew 8-bit differential clock driver which is designed to select between two separate differential clock inputs. The low output to output skew (< 50 ps) is maintained for either clock input. A LOW on the select pin (SEL) selects CLKINA, CLKINA and a HIGH on the SEL pin selects the CLKINB, CLKINB inputs. The 100310 is ideal for those applications that need the ability to freely select between two clocks, or to maintain the ability to switch to an alternate or backup clock should a problem arise with the primary clock source. A VBB output is provided for single-ended operation.
Features
s Low output to output skew s Differential inputs and outputs s Allows multiplexing between two clock inputs s Voltage compensated operating range: (PLCC package only) -4.2V to -5.7V s Available to industrial grade temperature range
Ordering Code:
Order Number 100310QC 100310QI Package Number V28A V28A Package Description 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
28-Pin PLCC
Pin Descriptions
Pin Names CLKINn, CLKINn SEL CLK07, CLK08 VBB NC Select Differential Clock Outputs VBB Output No Connect Description Differential Clock Inputs
Truth Table
CLKINA CLKINA CLKINB CLKINB SEL CLKn CLKn H L X X L H X X X X H L X X L H L L H H H L H L L H L H
© 1999 Fairchild Semiconductor Corporation
DS010943
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100310
Absolute Maximum Ratings(Note 1)
Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Pin Potential to Ground Pin (VEE) Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) -65°C to +150°C +150 °C -7.0V to +0.5V VEE to +0.5V -50 mA 2000V
Recommended Operating Conditions
Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0°C to +85°C -40°C to +85°C -5.7V to -4.2V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version DC Electrical Characteristics (Note 3)
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = 0°C to +85°C
Symbol VOH VOL VOHC VOLC VBB VDIFF VCM VIH VIL IIL IIH ICBO IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Output Reference Voltage Input Voltage Differential Common Mode Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Input Leakage Current Power Supply Current -10 -100 -40 -1380 150 VCC - 2.0 -1165 -1830 0.50 240 VCC - 0.5 -870 -1475 -1320 M in -1025 -1830 -1035 -1610 -1260 Typ -955 -1705 Max -870 -1620 Units mV mV mV mV mV mV V mV mV µA µA µA mA Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) VIN = VIH (Max) VIN = VEE Inputs Open Conditions VIN = VIH (Max) or VIL (Min) VIN = VIH or VIL (Max) IVBB = -250 µA Required for Full Output Swing Loading with 50 to -2.0V Loading with 50 to -2.0V
Note 3: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
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100310
Commercial Version (Continued) AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol fMAX Parameter Max Toggle Frequency CLKIN A/B to Qn SEL to Qn tPLH tPHL Propagation Delay, CLKINn to CLKn Differential Single-Ended tPLH tPHL tPS tOSLH tOSHL tOST tS tH tTLH tTHL Propagation Delay, SEL to Output LH-HL Skew Gate-Gate Skew LH Gate-Gate Skew HL Gate-Gate LH-HL Skew Setup Time SEL to CLKINn Setup Time SEL to CLKINn Transition Time 20% to 80%, 80% to 20% 300 0 275 510 750 0.80 0.80 0.75 0.90 0.96 0.99 10 20 20 30 1.00 1.20 1.20 30 30 50 60 300 0 275 500 750 0.82 0.82 0.80 0.92 0.98 1.02 10 20 20 30 1.02 1.22 1.25 30 50 50 60 300 0 275 480 750 0.89 0.89 0.85 1.01 1.06 1.10 10 20 20 30 1.09 1.29 1.35 30 50 50 60 ps ps ps Figure 4 ps ns Figure 2 (Note 4)(Note 7) (Note 5)(Note 7) (Note 5)(Note 7) (Note 6)(Note 7) ns Figure 3 750 575 750 575 750 575 MHz MHz TC = 0°C Min Typ Max M in TC = +25°C Typ Max Min TC = +85°C Typ Max Units Conditions
Note 4: tPS describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's LOW-to-HIGH and HIGH-to-LOW propagation delays. With differential signal pairs, a LOW-to-HIGH or HIGH-to-LOW transition is defined as the transition of the true output or input pin. Note 5: tOSLH describes in-phase gate-to-gate differential propagation skews with all differential outputs going LOW-to-HIGH; tOSHL describes the same conditions except with the outputs going HIGH-to-LOW. Note 6: tOST describes the maximum worst case difference in any of the tPS, tOSLH or tOST delay paths combined. Note 7: The skew specifications pertain to differential I/O paths.
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100310
Industrial Version DC Electrical Characteristics (Note 8)
VEE = -4.2V to -5.7V, VCC = VCCA = GND
Symbol VOH VOL VOHC VOLC VBB VDIFF VCM VIH VIL IIL IIH ICBO IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Output Reference Voltage Input Voltage Differential Common Mode Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Input Leakage Current Power Supply Current -10 -100 -40 -1395 150 -1170 -1830 0.50 240 -10 -100 -40 -870 -1480 TC = -40°C Min -1085 -1830 -1095 -1565 -1255 -1380 150 -1165 -1830 0.50 240 -870 -1475 Max -870 -1575 TC = 0°C to +85°C Min -1025 -1830 -1035 -1610 -1260 Max -870 -1620 Units mV mV mV mV mV mV V mV mV µA µA µA mA Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) VIN = VIH (Max) VIN = VEE Inputs Open Conditions VIN = VIH (Max) or VIL (Min) VIN = VIH or VIL (Min) IVBB = -250 µA Required for Full Output Swing Loading with 50 to -2.0V Loading with 50 to -2.0V
VCC - 2.0 VCC - 0.5 VCC - 2.0 VCC - 0.5
Note 8: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol fMAX Parameter Max Toggle Frequency CLKIN A/B to Qn SEL to Qn tPLH tP H L Propagation Delay, CLKINn, to CLKn Differential Single-Ended tPLH tP H L tP S tOSLH tOSHL tOST tS tH tTLH tT HL Propagation Delay SEL to Output LH-HL Skew Gate-Gate Skew LH Gate-Gate Skew HL Gate-Gate LH-HL Skew Setup Time SEL to CLKINn Setup Time SEL to CLKINn Transition Time 20% to 80%, 80% to 20% 300 0 275 510 750 0.78 0.78 0.70 0 .88 0 .95 0.99 10 20 20 30 0.98 1.18 1.20 30 50 50 60 300 0 275 500 750 0.82 0.82 0.80 0 .92 0 .98 1.02 10 20 20 30 1.02 1.22 1.25 30 50 50 60 300 0 275 480 750 0.89 0.89 0.85 1 .01 1 .06 1.10 10 20 20 30 1.09 1.29 1.35 30 50 50 60 ps ps ps Figure 4 ps ns Figure 2 (Note 9)(Note 12) (Note 10)(Note 12) (Note 10)(Note 12) (Note 11)(Note 12) ns Figure 3 750 575 750 575 750 575 MHz MHz TC = -40°C Min Typ Max M in TC = +25°C Typ Max Min TC = +85°C Typ Max Units Conditions
Note 9: tPS describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's LOW-to-HIGH and HIGH-to-LOW propagation delays. With differential signal pairs, a LOW-to-HIGH or HIGH-to-LOW transition is defined as the transition of the true output or input pin. Note 10: tOSLH describes in-phase gate-to-gate differential propagation skews with all differential outputs going LOW-to-HIGH; tOSHL describes the same conditions except with the outputs going HIGH-to-LOW. Note 11: tOST describes the maximum worst case difference in any of the tPS, tOSLH or tOST delay paths combined. Note 12: The skew specifications pertain to differential I/O paths.
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100310
Test Circuit
Note: Shown for testing CLKIN to CLK1 in the differential mode. L1, L2, L3 and L4 = equal length 50 impedance lines. All unused inputs and outputs are loaded with 50 in parallel with 3 pF to GND. Scope should have 50 input terminator internally.
FIGURE 1. AC Test Circuit
Switching Waveforms
FIGURE 2. Propagation Delay, SEL to Outputs
FIGURE 3. Propagation Delay, CLKIN/CLKIN to Outputs
FIGURE 4. Transition Times
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