Details, datasheet, quote on part number: PD45128841G5-A80L-9JF
PartPD45128841G5-A80L-9JF
CategoryMemory => DRAM
Description128m-bit Synchronous DRAM 4-bank, LVTTL
CompanyElpida Memory
DatasheetDownload PD45128841G5-A80L-9JF datasheet
  

 

Features, Applications

Description

The 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). These products are packaged in 54-pin TSOP (II).

Features

Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge Pulsed interface Possible to assert random column address in every cycle Quad internal banks controlled by BA0(A13) and BA1(A12) Byte control (×16) by LDQM and UDQM Programmable Wrap sequence (Sequential / Interleave) Programmable burst length and full page) Programmable /CAS latency (2 and 3) Automatic precharge and controlled precharge CBR (Auto) refresh and self refresh ×8, ×16 organization Single 0.3 V power supply LVTTL compatible inputs and outputs 4,096 refresh cycles / 64 ms Burst termination by Burst stop command and Precharge command

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.

Document No. E0031N30 (Ver. 3.0) Date Published August 2001 CP (K) Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
NEC Memory Synchronous DRAM Memory density : 128M bits Low Power
Organization : x16 Number of banks and Interface : 4 banks, LVTTL

 

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Some Part number from the same manufacture Elpida Memory
PD45128841G5-A80LI-9JF 128m-bit Synchronous DRAM 4-bank, LVTTL
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E0404E41 DDR2 > EDE1104AASE * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional
E0852E20 • Double-data-rate architecture; two data transfers perclock cycle• The high-speed data transfer is realized by the 4 bitsprefetch pipelined architecture• Bi-directional differential data strobe
EBE41RE4AAHA * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data
EBE41RE4ABHA
EBE20AE4ABFA
EBE20RE4ABFA
EBE21AD4AGFB
EBE21RD4AEFA
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EBE10AD4AGFA
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EBE51AD8AGFA
EBE51RD8AEFA
EBE51RD8AGFA
EBE11UD8AEFA

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PD45128163-SU : 128m-bit Synchronous DRAM 4-bank, LVTTL

PD45128163G5-A75LT-9JF : 128m-bit Synchronous DRAM 4-bank, LVTTL

EBE10AD4AGFA-4A-E : * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver *

EBE11ED8AEFA-5C-E : * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver *

EDD5108AFTA : * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs

EDD5116AFTA : * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs

EDD2516AETA-5C-E : * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs

EBD52UC8AKFA-5B-E : 512mb Unbuffered DDR Sdram DIMM (64M Words x 64 Bits, 2 Ranks)

EDS6432AFTA : 64M bits Sdram (2M Words x 32 Bits)

 
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