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Details, datasheet, quote on part number:PD45128163G5-A80SU-9JF
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD45128441, 45128841, 45128163
128M-bit Synchronous DRAM 4-bank, LVTTL
Description
The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). These products are packaged in 54-pin TSOP (II).
Features
· Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge · Pulsed interface · Possible to assert random column address in every cycle · Quad internal banks controlled by BA0(A13) and BA1(A12) · Byte control (×16) by LDQM and UDQM · Programmable Wrap sequence (Sequential / Interleave) · Programmable burst length (1, 2, 4, 8 and full page) · Programmable /CAS latency (2 and 3) · Automatic precharge and controlled precharge · CBR (Auto) refresh and self refresh · ×4, ×8, ×16 organization · Single 3.3 V ± 0.3 V power supply · LVTTL compatible inputs and outputs · 4,096 refresh cycles / 64 ms · Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
Document No. E0031N30 (Ver. 3.0) Date Published August 2001 CP (K) Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
µPD45128441, 45128841, 45128163
Ordering Information
Part number Organization (word × bit × bank) 8M × 4 × 4 Clock frequency MHz (MAX.) 133 133 125 100 4M × 8 × 4 133 133 125 100 2M × 16 × 4 133 133 125 100 8M × 4 × 4 4M × 8 × 4 2M × 16 × 4 133 125 133 125 133 125 Package 54-pin Plastic TSOP (II) (10.16mm (400))
µPD45128441G5-A75A-9JF µPD45128441G5-A75-9JF µPD45128441G5-A80-9JF µPD45128441G5-A10-9JF µPD45128841G5-A75A-9JF µPD45128841G5-A75-9JF µPD45128841G5-A80-9JF µPD45128841G5-A10-9JF µPD45128163G5-A75A-9JF µPD45128163G5-A75-9JF µPD45128163G5-A80-9JF µPD45128163G5-A10-9JF µPD45128441G5-A75L-9JF µPD45128441G5-A80L-9JF µPD45128841G5-A75L-9JF µPD45128841G5-A80L-9JF µPD45128163G5-A75L-9JF µPD45128163G5-A80L-9JF
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Data Sheet E0031N30
µPD45128441, 45128841, 45128163
Part Number
[ x4, x8 ]
µPD45128841G5 - A75L
NEC Memory Synchronous DRAM Memory density 128 : 128M bits Low Power
Organization 4 : x4 8 : x8
Minimum cycle time 75A 75 80 10 : 7.5 ns (133 MHz @CL=2) : 7.5 ns (133 MHz @CL=3) : 8 ns (125 MHz) : 10 ns (100 MHz)
Number of banks 4 : 4 banks
Interface 1 : LVTTL
Low voltage A : 3.3 V ± 0.3 V
Package
[ x16 ]
Organization 16 : x16 Number of banks and Interface 3 : 4 banks, LVTTL
163
G5 : TSOP (II)
Data Sheet E0031N30
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