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Details, datasheet, quote on part number:HM5117805LTT-5
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Datasheet text preview:
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Description Features
HM5117805 Series
16 M EDO DRAM (2-Mword × 8-bit) 2 k Refresh
E0156H10 (Ver. 1.0) (Previous ADE-203-630D (Z)) Jun. 27, 2001
The HM5117805 is a C MOS dynamic R AM orga nize d 2, 097,152-w ord × 8-bit. It employs the most adva nce d C MOS tec hnology for high per forma nce and low powe r. The HM5117805 off ers Extende d Da ta Out (ED O) P age Mode as a high spee d ac ce ss mode. Multiplexe d addr ess input per mits the HM5117805 to be packaged in standard 28-pin plastic SOJ and 28-pin TSOP.
· Single 5 V (±10%) · Access time: 50 ns/60 ns/70 ns (max) · Power dissipation Active mode: 605 mW/550 mW/495 mW (max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) · EDO page mode capability · Long refresh period 2048 refresh cycles : 32 ms : 128 ms (L-version) · 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) · Battery backup operation (L-version)
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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HM5117805 Series
Ordering Information
Type No. Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 400-mil 28-pin plastic TSOP II (TTP-28DA) 300-mil 28-pin plastic SOJ (CP-28DNA) Package 400-mil 28-pin plastic SOJ (CP-28DA) HM5117805J-5 HM5117805J-6 HM5117805J-7
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HM5117805LJ-5 HM5117805LJ -6 HM5117805LJ -7 HM5117805S-5 HM5117805S-6 HM5117805S-7 HM5117805LS-5 HM5117805LS-6 HM5117805LS-7 HM5117805TT-5 HM5117805TT-6 HM5117805TT-7 HM5117805LTT-5 HM5117805LTT-6 HM5117805LTT-7 HM5117805TS-5 HM5117805TS-6 HM5117805TS-7 HM5117805LTS-5 HM5117805LTS-6 HM5117805LTS-7 2
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50 ns 60 ns 70 ns 50 ns 60 ns 70 ns
Data Sheet E0156H10
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300-mil 28-pin plastic TSOP II (TTP-28DB)
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HM5117805 Series
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VCC I/O0 I/O1 I/O2 I/O3 RE W AS NC A10 A0 A1 A2 A3 VCC
Pin Arrangement
HM5117805J/LJ Series HM5117805S/LS Series
1 2 3 4 5 6 7 8 9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4
HM5117805TT/LTT Series HM5117805TS/LTS Series VCC I/O0 I/O1 I/O2 I/O3 RE W AS NC A10 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4 O CAS AE 9 A8 A7 A6 A5 A4 VSS
Pin Description
Pin name A0 to A10 Function Address input -- Row/Refresh address A0 to A10 -- Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection
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O CAS E A9 A8 A7 A6 A5 A4 10 11 12 13 14 VSS
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VCC
(Top view)
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3
I/O0 to I/O7 RAS CAS WE OE VCC VSS NC
Data Sheet E0156H10
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