|Description||3.3v Bit Error Rate Tester Bert|
|Datasheet||Download DS2172T datasheet
Generates/detects digital bit patterns for analyzing, evaluating and troubleshooting digital communications systems Operates at speeds from to 20 MHz Programmable polynomial length and feedback taps for generation of any other pseudorandom pattern to 32 bits in length including: and 232-1 Programmable user-defined pattern and length for generation of any repetitive pattern to 32 bits in length Large 32-bit error count and bit count registers Software programmable bit error insertion Fully independent transmit and receive sections 8-bit parallel control port Detects test patterns with bit error rates to 10-2TDATA TDIS TCLK VSS VDD RCLK RDIS RDATA
The DS21372 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver, and analyzer capable of meeting the most stringent error performance requirements of digital transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive) conform to CCITT/ITU O.152, O.153, and O.161 standards. The DS21372 operates at clock rates ranging from to 20 MHz. This wide range of operating frequency allows the to be used in existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs, Routers, Bridges, CSUs, DSUs, and CPE equipment. The DS21372 user-programmable pattern registers provide the unique ability to generate loopback patterns required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS21372 can initiate the loopback, run the test, check for errors, and finally deactivate the loopback. The DS21372 consists of four functional blocks: the pattern generator, pattern detector, error counter, and control interface. The DS21372 can be programmed to generate any pseudorandom pattern with length to 232-1 bits (see Table 5, Note 9) or any user programmable bit pattern from to 32 bits in length. Logic inputs can be used to configure the DS21372 for applications requiring gap clocking such FractionalT1, Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the DS21372 can insert single to 10-7 bit errors to verify equipment operation and connectivity.
The DS21372 is programmed to generate a particular test pattern by programming the following registers: Pattern Set Registers (PSR) Pattern Length Register (PLR) Polynomial Tap Register (PTR) Pattern Control Register (PCR) Error Insertion Register (EIR)
Please see Tables 4 and 5 for examples of how to program these registers in order to generate some standard test patterns. Once these registers are programmed, the user will then toggle the TL (Transmit Load) bit or pin to load the pattern into the onboard pattern generation circuitry and the pattern will begin appearing at the TDATA pin.
The DS21372 expects to receive the same pattern that it transmitted. The synchronizer examines the data at RDATA and looks for characteristics of the transmitted pattern. The user can control the onboard synchronizer with the Sync Enable and Resync bits in the Pattern Control Register. In pseudorandom mode, the received pattern is tested to see if it fits the polynomial generator as defined in the transmit side. For pseudorandom patterns, only the original pattern and an all ones pattern or an all 0s pattern will satisfy this test. Synchronization in pseudorandom pattern mode should be qualified by using the RA1 and RA0 indicators in the Status Register. Synchronization is declared after + n bits are received without error, where n is the exponent in the polynomial from Table 4. Once in synchronization = 1) any deviation from this pattern will be counted by the Bit Error Count Register. In repetitive pattern mode a received pattern of the same length as being transmitted will satisfy this test. Synchronization in repetitive pattern mode should be qualified by using the RA1 and RA0 indicators in the Status Register and examining the Pattern Receive Register (PRR0--3). See section 10 for an explanation of the Pattern Receive Register. Once in synchronization = 1) any deviation from this pattern will be counted by the Bit Error Count Register.
Users can calculate the actual Bit Error Rate (BER) of the digital communications channel by reading the bit error count out of the Bit Error Count Register (BECR) and reading the bit count out of the Bit Count Register (BCR) and then dividing the BECR value with the BCR value. The user has total control over the integration period of the measurement. The LC (Load Count) bit or pin is used to set the integration period.
Via the Error Insertion Register (EIR), the user can intentionally inject a particular error rate into the transmitted data stream. Injecting errors allows users to stress communication links and to check the functionality of error monitoring equipment along the path.
On power-up, the registers in the DS21372 will in a random state. The user must program all the internal registers to a known state before proper operation can be insured.
1. Tap A always equals length (N-1) of pseudorandom or repetitive pattern. 2. Tab B can be programmed to any feedback tap for pseudorandom pattern generation.
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