Details, datasheet, quote on part number: C8051F005
PartC8051F005
CategoryMicrocontrollers => System On Chip
TitleSystem On Chip
DescriptionMixed-signal 32KB Isp Flash MCU
CompanyCygnal Integrated
DatasheetDownload C8051F005 datasheet
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Features, Applications

C8051F015/6/7) 1LSB INL; No Missing Codes Programmable Throughput to 8 External Inputs; Programmable as SingleEnded or Differential Programmable Amplifier Gain: Data Dependent Windowed Interrupt Generator Built-in Temperature Sensor 3C)

Pipelined Instruction Architecture; Executes 70% of Instruction Set or 2 System Clocks to 25MIPS Throughput with 25MHz Clock 21 Vectored Interrupt Sources 256 Bytes Internal Data RAM (F000/01/02/10/11/12) 2304 Bytes Internal Data RAM (F005/06/07/15/16/17) 32k Bytes FLASH; In-System Programmable in 512 byte Sectors 4 Byte-Wide Port I/O; All are 5V tolerant Hardware SMBusTM (I2CTM Compatible), SPITM, and UART Serial Ports Available Concurrently Programmable 16-bit Counter/Timer Array with Five Capture/Compare Modules Four General Purpose 16-bit Counter/Timers Dedicated Watch-Dog Timer Bi-directional Reset Internal Programmable Oscillator: 2-to-16MHz External Oscillator: Crystal, RC,C, or Clock Can Switch Between Clock Sources on-the-fly; Useful in Power Saving Modes Typical Operating Current: @ 25MHz Multiple Power Saving Sleep and Shutdown Modes

Programmable Hysteresis Values Configurable to Generate Interrupts or Reset 2.4V; 15 ppm/C Available on External Pin

On-Chip Debug Circuitry Facilitates Full Speed, NonIntrusive In-System Debug (No Emulator Required!) Provides Breakpoints, Single Stepping, Watchpoints, Stack Monitor Inspect/Modify Memory and Registers Superior Performance to Emulation Systems Using ICEChips, Target Pods, and Sockets IEEE1149.1 Compliant Boundary Scan Low Cost Development Kit

8051 CPU CLOCK DEBUG JTAG (25MIPS) CIRCUIT CIRCUITRY B 21 SANITY ISP FLASH SRAM INTERRUPTS CONTROL

Table 1.1. Product Selection Guide................................................................................................................... 8 Figure 1.1. C8051F000/05/10/15 Block Diagram............................................................................................. 9 Figure 1.2. C8051F001/06/11/16 Block Diagram........................................................................................... 10 Figure 1.3. C8051F002/07/12/17 Block Diagram........................................................................................... 1.1. CIP-51TM CPU...................................................................................................................................... 12 Figure 1.4. Comparison of Peak MCU Execution Speeds............................................................................... 12 Figure 1.5. On-Board Clock and Reset........................................................................................................... 13 1.2. On-Board Memory................................................................................................................................ 14 Figure 1.6. On-Board Memory Map............................................................................................................... 14 1.3. JTAG Debug and Boundary Scan......................................................................................................... 15 Figure 1.7. Debug Environment Diagram....................................................................................................... 15 1.4. Programmable Digital I/O and Crossbar............................................................................................... 16 Figure 1.8. Digital Crossbar Diagram............................................................................................................. 16 1.5. Programmable Counter Array............................................................................................................... 17 Figure 1.9. PCA Block Diagram..................................................................................................................... 17 1.6. Serial Ports............................................................................................................................................ 17 1.7. Analog to Digital Converter.................................................................................................................. 18 Figure 1.10. ADC Diagram............................................................................................................................. 18 1.8. Comparators and DACs......................................................................................................................... 19 Figure 1.11. Comparator and DAC Diagram.................................................................................................. 19

ABSOLUTE MAXIMUM RATINGS*............................................................................ 20 GLOBAL DC ELECTRICAL CHARACTERISTICS.................................................. 20 PINOUT AND PACKAGE DEFINITIONS.................................................................... 21

Table 4.1. Pin Definitions............................................................................................................................... 21 Figure 4.1. TQFP-64 Pinout Diagram............................................................................................................. 23 Figure 4.2. TQFP-64 Package Drawing.......................................................................................................... 24 Figure 4.3. TQFP-48 Pinout Diagram............................................................................................................. 25 Figure 4.4. TQFP-48 Package Drawing.......................................................................................................... 26 Figure 4.5. LQFP-32 Pinout Diagram............................................................................................................. 27 Figure 4.6. LQFP-32 Package Drawing.......................................................................................................... 28

Figure 5.1. 12-Bit ADC Functional Block Diagram........................................................................................ 29 5.1. Analog Multiplexer and PGA................................................................................................................ 29 5.2. ADC Modes of Operation..................................................................................................................... 30 Figure 5.2. 12-Bit ADC Track and Conversion Example Timing................................................................... 30 Figure 5.3. Temperature Sensor Transfer Function......................................................................................... 31 Figure 5.4. AMX0CF: AMUX Configuration Register (C8051F00x)............................................................ 31 Figure 5.5. AMX0SL: AMUX Channel Select Register (C8051F00x)........................................................... 32 Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x)................................................................. 33 Figure 5.7. ADC0CN: ADC Control Register (C8051F00x).......................................................................... 34 Figure 5.8. ADC0H: ADC Data Word MSB Register (C8051F00x)............................................................. 35 Figure 5.9. ADC0L: ADC Data Word LSB Register 35 5.3. ADC Programmable Window Detector................................................................................................. 36 Figure 5.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F00x)................................... 36 Figure 5.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F00x).................................... 36 Figure 5.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F00x)........................................ 36 Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x)......................................... 36 Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data................................................. 37 Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data................................................... 37 Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data................................................... 38

Table 5.1. 12-Bit ADC Electrical Characteristics........................................................................................... 38 Table 5.1. 12-Bit ADC Electrical Characteristics........................................................................................... 39

Figure 6.1. 10-Bit ADC Functional Block Diagram........................................................................................ 40 6.1. Analog Multiplexer and PGA................................................................................................................ 40 6.2. ADC Modes of Operation..................................................................................................................... 41 Figure 6.2. 10-Bit ADC Track and Conversion Example Timing................................................................... 41 Figure 6.3. Temperature Sensor Transfer Function......................................................................................... 42 Figure 6.4. AMX0CF: AMUX Configuration Register (C8051F01x)............................................................ 42 Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x)........................................................... 43 Figure 6.6. ADC0CF: ADC Configuration Register (C8051F01x)................................................................. 44 Figure 6.7. ADC0CN: ADC Control Register (C8051F01x).......................................................................... 45 Figure 6.8. ADC0H: ADC Data Word MSB Register (C8051F01x)............................................................. 46 Figure 6.9. ADC0L: ADC Data Word LSB Register 46 6.3. ADC Programmable Window Detector................................................................................................. 47 Figure 6.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F01x)................................... 47 Figure 6.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F01x).................................... 47 Figure 6.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F01x)........................................ 47 Figure 6.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F01x)......................................... 47 Figure 6.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data................................................. 48 Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data................................................... 48 Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data................................................... 49 Table 6.1. 10-Bit ADC Electrical Characteristics........................................................................................... 49 Table 6.1. 10-Bit ADC Electrical Characteristics........................................................................................... 50

Figure 7.1. DAC Functional Block Diagram.................................................................................................... 51 Figure DAC0H: DAC0 High Byte Register............................................................................................. 52 Figure DAC0L: DAC0 Low Byte Register.............................................................................................. 52 Figure DAC0CN: DAC0 Control Register............................................................................................... 52 Figure DAC1H: DAC1 High Byte Register............................................................................................. 53 Figure DAC1L: DAC1 Low Byte Register.............................................................................................. 53 Figure DAC1CN: DAC1 Control Register............................................................................................... 53 Table 7.1. DAC Electrical Characteristics...................................................................................................... 54

Figure 8.1. Comparator Functional Block Diagram........................................................................................ 55 Figure 8.2. Comparator Hysteresis Plot.......................................................................................................... 56 Figure 8.3. CPT0CN: Comparator 0 Control Register.................................................................................... 57 Figure 8.4. CPT1CN: Comparator 1 Control Register.................................................................................... 58 Table 8.1. Comparator Electrical Characteristics............................................................................................ 59

Figure 9.1. Voltage Reference Functional Block Diagram............................................................................. 60 Figure 9.2. REF0CN: Reference Control Register.......................................................................................... 61 Table 9.1. Reference Electrical Characteristics............................................................................................... 61

Figure 10.1. CIP-51 Block Diagram............................................................................................................... 62 10.1. INSTRUCTION SET........................................................................................................................ 63 Table 10.1. CIP-51 Instruction Set Summary.................................................................................................. 64 10.2. MEMORY ORGANIZATION.......................................................................................................... 67 Figure 10.2. Memory Map.............................................................................................................................. 68 10.3. SPECIAL FUNCTION REGISTERS............................................................................................... 69 Table 10.2. Special Function Register Memory Map...................................................................................... 69 Table 10.3. Special Function Registers........................................................................................................... 69 Figure 10.3. SP: Stack Pointer........................................................................................................................ 73 Figure 10.4. DPL: Data Pointer Low Byte...................................................................................................... 73 CYGNAL Integrated Products, Inc. 2002


 

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