Details, datasheet, quote on part number: ADDS-2111-EZ-KIT
PartADDS-2111-EZ-KIT
Category
DescriptionADSP-2100 Family Development Tools
CompanyAnalog Devices
DatasheetDownload ADDS-2111-EZ-KIT datasheet
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Features, Applications
FEATURES

LINKER Maps Assembler Output to Target System Memory Supports User-Defined Library Routines Creates Memory Map Listing PROM SPLITTER & HOST PROCESSOR PORT (HIP) SPLITTER Generates PROM Programmer Compatible Files in a Variety of Industry-Standard Formats Executable File for Programming PROMs or for Host Processor Booting

SYSTEM BUILDER Defines Architecture of ADSP-21xx System Specifies Amount of RAM/ROM Memory ASSEMBLER Easy-to-Program, Algebraic Instruction Syntax Supports C Language Constructs Provides Flexible Macro Processing Encourages Modular Code Development

ANSI C COMPILER LIBRARIES LINKER EXECUTABLE FILE
STEP 3: DEBUG SOFTWARE STEP 4: DEBUG IN TARGET SYSTEM STEP 5: MANUFACTURE FINAL SYSTEM
EZ-LAB DEVELOPMENT BOARD OR THIRD-PARTY PC PLUG-IN CARDS

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703

SIMULATOR Features Reconfigurable GUI (Graphical User Interface) Supports Full Symbolic Disassembly and On-Line Assembly Provides Breakpoint and Single-Step Execution Includes CBUGTM C Source-Level Debugger as Integrated Tool Supports Multiple Break Conditions Provides Full View of All Processor Registers and Memory for Direct Modification of Contents Profiles Code Execution History Uses Data Files to Simulate Parallel I/O Ports, Serial Ports, HIPs, and Analog I/O Interface Plots Data Memory Graphically G21 OPTIMIZING C COMPILER & C RUNTIME LIBRARY Compliant with ANSI C Standards Includes C-Callable Library of ANSI-Standard and DSP Functions Supports In-Line Assembly Code Using asm Construct Incorporates Optimizing Algorithms Generates Reliable and ROM-able Code Simplifies Interrupt Handling via Library Functions Provides Support for Heap Memory Management Supports Switches Used by the ADSP-21000 Family G21K Floating Point C Compiler Supports Float Type IEEE-Single Precision Math Routines CBUG C SOURCE-LEVEL DEBUGGER Supports Single Step Execution Supports Breakpoints Integrated with Simulators and EZ-ICE Emulators

DEVELOPMENT HARDWARE TOOLS EZ-LAB EVALUATION BOARD Complete Hardware Platform with Memory and I/O Preprogrammed with DSP Demo Programs Contains Audio/Voice I/O Port with Microphone Input and Powered Output for Speaker Memory Expansion and I/O from Bus Expansion Connector Serial Port Interface via SPORT Connector EZ-KIT STARTER PACKAGES Complete Hardware and Software Development Kit Includes an EZ-LAB Evaluation Board and ADSP-2100 Family Assembler/Linker and Simulator Software for IBM PC EZ-KIT LITE Low Cost Development System Including Hardware and Software MS Windows 3.1 Based Monitor Includes a Variety of Demonstration Programs with Source Code Development Platform for all ADSP-21xx Processors Audio Input/Output and Expansion Connectors EZ-ICE EMULATOR Performs Full-Speed, In-Circuit Emulation of ADSP-21xx Target Systems Software Uses Same GUI (Graphical User Interface) as Simulator for Easier Debugging Control Single-Step Capability Stand Alone Operation for Software Debugging Upload/Download Memory with IBM PC 3-VOLT EMULATION CONVERTER BOARD Used with the ADSP-2101 EZ-ICE to Enable Emulation with (3 V) Target System

CBUG is a trademark of Analog Devices, Inc. EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc

The ADSP-2100 Family Development Software, a complete set of software design tools, lets you program applications for this family of DSP microprocessors that includes the ADSP-2111, ADSP-2115, and the newest members, the ADSP-2171 and ADSP-2181. With these tools, an EZ-ICE In-Circuit Emulator, and an EZ-LAB Evaluation Board, you can quickly and efficiently design your DSP applications. The figure on page 1 ("System Development Process Overview") shows how the tools are typically used in the development process.

The ADSP-2100 Family hardware development tools provide a controlled environment for observing, debugging, and testing activities in a full-speed target system. Our ADSP-2100 Family EZ-ICE Emulators provide this control by replacing the target processor or, in the case of the ADSP-2181, by assuming control of the DSP through its ICE-Port. The EZ-ICE, controlled by an IBM PC host computer, using a GUI interface similar to the ADSP-2100 Family Simulators, lets you examine and modify processor information such as registers and memory. The ADSP-2100 Family EZ-LAB Evaluation Boards let you test coded applications in real time without a host or PC. At reset, the processor on the ADSP-2100 Family EZ-LAB boots code and program memory into its internal program memory from the EPROM, and then executes the code. EZ-KIT offers a complete development environment including the ADSP-2100 Family Assembler/Linker and Simulator, an ADSP-2100 Family EZ-LAB Evaluation Board. The EZ-KITs for the ADSP-2101 and ADSP-2111 include an applications handbook (Digital Signal Processing Applications Using the ADSP-2100 Family Applications), plus a laboratory textbook (Digital Signal Processing Laboratory Using the ADSP-2101 Microcomputer Laboratory Workbook with Introductory DSP Experiments) and source code diskettes. The EZ-KIT Lite for the is a lower cost starter kit that includes a subset of the regular EZ-KIT software and documentation.

The software development tools include the following programs: System Builder G21 C Compile Assembler C Runtime Library Linker CBUG C Source-Level Debugger Simulator PROM Splitter The System Builder reads your system specification file and then generates an architecture description file that passes information about your target hardware to the linker, simulator, and emulator. Code generation begins with the creation of C language and/or assembly language source code modules. These modules are compiled/assembled separately and then linked together to form an executable program (memory image file). The highly readable algebraic syntax of the ADSP-2100 Family instruction set eases programming in assembly language. Multiplyaccumulate instructions are written in the same manner as the actual equation. For example, the algebraic statement x*y is coded in assembly language + MX0*MY0. The simulator configures program and data memory according to the architecture description file and simulates the memorymapped I/O ports to let you debug your system and analyze its performance. After simulating your system and software, use the emulator with your prototype hardware to test circuitry, timing, and real-time software execution. The PROM Splitter then translates the linker-output executable file into an industrystandard file format for a PROM programmer. Once you burn the code into a PROM device and plug an ADSP-21xx processor to the target board, your prototype is ready to run. Development software is available for the IBM (or IBMcompatible) PC/AT and Sun4 workstation platforms.

The System Builder lets you define system hardware based on ADSP-21xx processors with memory that can be specified as RAM or ROM. It also lets you design ADSP-21xx Family systems with paged external data memory, extending the processor's address space for additional data storage.

The G21 C Compiler is an optimizing ANSI compiler based on the GNU gcc compiler. Applications written in C are compiled, assembled, and linked to create executable ADSP-21xx programs that can be debugged with an ADSP-21xx Simulator or Emulator. It also supports in-line assembly code using the asm( ) construct, which lets you use C expressions. The G21 C Compiler contains optimization features to increase execution speed of the resultant assembly code. These features include algorithms to perform the following: Constant Folding Common Subexpression Elimination Loop Optimization and Strength Reduction Global and Local Register Allocation Parallelization Instruction Scheduling

EZ-ICE Emulators EZ-KIT Development Tools Packages EZ-LAB Evaluation Boards

 

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