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Details, datasheet, quote on part number:M24C04-MN6
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Datasheet text preview:
M24C16, M24C08 M24C04, M24C02, M24C01
16K/8K/4K/2K/1K SERIAL I2C BUS EEPROM
PRELIMINARY DATA
TWO WIRE I2C SERIAL INTERFACE SUPPORTS 400kHz PROTOCOL 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION 2ms TYPICAL PROGRAMMING TIME SINGLE SUPPLY VOLTAGE: 4.5V to 5.5V for M24Cxx 2.5V to 5.5V for M24Cxx-W 1.8V to 3.6V for M24Cxx-R HARDWARE WRITE CONTROL BYTE and PAGE WRITE (up to 16 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH-UP PERFORMANCES DESCRIPTION The M24C16/C08/C04/C02/C01 specification covers a range of 16K/8K/4K/2K/1K bit serial I2C EEPROM products respectively. The memory is an e l e c t r i c a l l y erasable programmable memory (EEPROM) fabricated with SGS-THOMSON's High Endurance Single Polysilicon CMOS technology which guarantees an endurance typically well above one million erase/write cycles with a data retention of 40 years. The "-W" version operate with a power supply value as low as 2.5V and the "-R" version operate down to 1.8V. Plastic Dual In-line, Plastic Small Outline and Thin Shrink Small Outline Packages are available. Table 1. Signal Names
E0-E2 SDA SCL WC VCC VSS February 1998 Chip Enable Inputs Serial Data Address Input/Output Serial Clock Write Control Supply Voltage Ground
8 1
PSDIP8 (BN) 0.25mm Frame
8 1
SO8 (MN) 150mil Width
8 1
TSSOP8 (DW) 169mil Width
Figure 1. Logic Diagram
VCC
3 E0-E2 SCL WC M24Cxx SDA
VSS
AI02033
1/17
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M24C16, M24C08, M24C04, M24C02, M24C01
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TLEAD Parameter Ambient OperatingTemperature Storage Temperature Lead Temperature, Soldering (PSDIP8 package) (SO8 package) (TSSOP8 package) 10 sec 40 sec t.b.c.
(2)
Value 40 to 125 65 to 150 260 215 t.b.c. 0.6 to 6.5 0.3 to 6.5
(3)
Unit °C °C °C V V V V
VIO VCC VESD
Input or Output Voltages Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model)
(4)
4000 500
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. Depends on range. 3. MIL-STD-883C, 3015.7 (100pF, 1500 ). 4. EIAJ IC-121 (Condition C) (200pF, 0 ).
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
M24Cxx E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI02034
M24Cxx VCC WC SCL SDA E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI02035
VCC WC SCL SDA
Figure 2C. TSSOP Pin Connections
Figure 2D. TSSOP Pin Connections
M24C01 M24C02 M24C04 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI02036
M24C08 M24C16
VCC WC SCL SDA
WC VCC NC NC
1 2 3 4
8 7 6 5
AI02216
SCL SDA VSS E2/NC
Warning: NC = Not Connected. Pin 5 is E2 for M24C08 and NC for M24C16. 2/17
M24C16, M24C08, M24C04, M24C02, M24C01
Table 3. Device Select Code
Device Code Bit M24C01 M24C02 M24C04 M24C08 M24C16 b7 1 1 1 1 1 b6 0 0 0 0 0 b5 1 1 1 1 1 b4 0 0 0 0 0 b3 E2 E2 E2 E2 A10 Chip Enable b2 E1 E1 E1 A9 A9 b1 E0 E0 A8 A8 A8 RW b0 RW RW RW RW RW
Notes: 1. E0, E1,E2 correspond respectively to Pin 1, 2, 3 of the memories. 2. A10, A9, A8 correspond to the MSB of the memory array address word.
Table 4. Operating Modes (1)
Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write
Note: 1. X = VIH or VIL.
RW bit '1' '0' '1' '1' '0' '0'
WP X X X X VIL VIL
Data Bytes 1 1 1 1 16
Initial Sequence START, Device Select, RW = '1' START, Device Select, RW = '0', Address, reSTART, Device Select, RW = '1' As CURRENT or RANDOM Mode START, Device Select, RW = '0' START, Device Select, RW = '0'
DESCRIPTION (cont'd) The memory is compatible with the I2C standard, two wire serial interface which uses a bi-directional data bus and serial clock. The memory carry a built-in 4 bit unique Device Type Identifier code (1010) which corresponds to the I2C bus definition. This Device Type Identifier code is used together with 3 Chip Enable bits. Depending on the size of the device memory, these Chip Enables bits can be directly linked to the E0-E1-E2 input pins or can be used as Most Significant Address bits for the memory area. The I2C protocol allows to address up to 16K bits of memory on the same bus. Using the E0-E1-E2 inputs pins, up to eight M24C01/C02, four M24C04, two M24C08 or one M24C16 device can be connected to the same I2C bus (see Chip Enable paragraph below). For more details about the usage of these 3 Chip Enable bits, refer to Table 3, Device Select Code description. The memory behaves as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by the Device Select Code which is composed by a stream of 7 bits (Device Type Identifier code '1010' followed by the 3 Chip Enable bits), plus one read/write bit (RW) and terminated by an acknowledge bit.
When writing data to the memory, it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition after an Ack for WRITE and after a NoAck for READ. Power On Reset: VCC lock out write protect. In order to prevent any possible data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. SIGNAL DESCRIPTIONS Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3).
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