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Part: 74VHC374T
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Datasheet: Download 74VHC374T datasheet File size : 110 kB
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74VHC374
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
s s s
s
s s
s
s
s
s s
HIGH SPEED: fMAX = 185 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 IMPROVED LATCH-UP IMMUNITY LOW NOISE VOLP = 0.9V (Max.)
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74VHC374M 74VHC374T On the positive t ransition o f the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high o r low logic level) and while high level the outputs will be in a high impedance state. The output control does no t affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against s tatic discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The 74VHC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It has similar high speed performance of equivalent Bipolar Schottky TTL combined with true CMOS low power dissipation. This 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE). PIN CONNECTION AND IEC LOGIC SYMBOLS
September 1998
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74VHC374
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
P I N No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 S YMB O L OE Q0 to Q7 NAM E AN D F UNC T I O N 3 Sta te Outp ut Enable In put ( Act iv e LO W) 3 Sta te Outp ut s
D0 to D7
D at a Inp ut s
CLOCK GND VCC
C lock In put (LO W t o H IG H, edge tr iggere d) G ro und (0 V) P os itiv e S upply V olt age
TRUTH TABLE
I N P UT S OE H L L L
X: Don't care Z: High impedance
O UT P UT S D X X L H Q Z NO CHANGE L H
CK X
LOGIC DIAGRAM
2/10
74VHC374
ABSOLUTE MAXIMUM RATINGS
S y mb o l VCC VI VO II K IOK IO Tstg TL Supply Vo lt age DC In put Volta ge DC Ou tpu t Vo lt age DC In put Diode Curr ent DC Ou tpu t D iode C u rrent DC Ou tpu t C urrent Stor age T emperat ur e Lead T empe ratu re (10 se c) P arame t er V al u e -0.5 to + 7.0 -0.5 to + 7.0 -0.5 t o VCC + 0.5 - 20 ± 20 ± 25 ± 75 -65 to +150 300 Un i t V V V mA mA mA mA
o o
ICC or IGND DC VCC or Gro und Current
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
S y mb o l VCC VI VO Top dt/dv Supply Vo lt age Inp ut Volta ge Out put V oltage Ope rat ing T empe ratu re Inp ut Rise a nd Fa ll T im e ( s ee not e 1) (VCC = 3.3 ± 0. 3V) (VCC = 5.0 ± 0.5 V ) P arame t er Va lu e 2.0 to 5.5 0 to 5.5 0 to VCC -40 to +85 0 to 100 0 to 20 Un i t V V V
o
C
ns/V ns/V
1) VIN from 30% to 70% of VCC
DC SPECIFICATIONS
S ym b o l P ar amet e r T est Co n d i t i o n s V CC ( V) VIH VIL VOH High Level I nput Volt age Low L evel Input Volt age High Level O ut put Volt age 2. 0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 VOL Low L evel Outp ut Volt age 2.0 3.0 4. 5 3.0 4.5 IOZ II ICC 3 St a te O utp ut Leakage C u rrent Input Leakage C urrent Quies cent Supply Current 5. 5 0 to 5.5 5.5 VI = V I H or VIL
(*) o
V al u e TA = 25 C M in. 1.5 0.7VCC 0.5 0.3V CC T yp . M ax. - 40 t o 85 C Mi n. 1.5 0.7V CC 0.5 0.3V CC 1.9 2.9 4.4 2.48 3.8 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 ±0.25 ±0.1 4 0.1 0.1 0.1 0.44 0.44 ± 2.5 ± 1.0 40 M ax.
o
Unit
V V
IO=-50 µA VI(*) = V I H or VIL IO=-50 µA IO=-50 µA IO=-4 mA IO=-8 mA IO=50 µA IO=50 µA IO=50 µA IO=4 mA IO=8 mA VI = VIH or VIL VO = VCC or GND VI = 5.5V or GN D VI = VCC or GND
1.9 2.9 4.4 2.58 3.94
2.0 3.0 4.5
V
V
µA µA µA
(*) All outputs loaded.
3/10
74VHC374
AC ELECTRICAL CHARACTERISTICS (Input tr = tf =3 ns)
S ym b o l P ar amet e r V CC ( V) tPLH tPHL Propagati on D e lay Tim e CK to Q T e st Co n d i t i o n CL ( pF) 15 50 15 50 15 50 15 50 50 50 RL = RL = RL = RL = RL = RL = 1K 1K 1K 1K 1K 1K V al u e o TA = 25 C M i n . T yp . M ax. 8.1 12.7 10.6 16.2 5.4 8.1 6.9 10.1 7.1 9.6 5.1 6.6 10.2 6.1 11.0 14.5 7.6 9.6 14.0 8.8 5.0 5.0 4.5 3.0 2.0 2.0 60 100 50 50 250 270 1.5 1.0 60 100 1.5 1.0 Unit - 40 t o Mi n. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 85 C M ax. 15.0 18.5 9.5 11.5 13.0 16.5 9.0 11.0 16.0 10.0 5.5 5.0 4.5 3.0 2.0 2.0
o
3.3 (*) 3.3 ( **) 5.0 5.0( **) 3.3 (*) 3.3 ( **) 5.0 ( **) 5.0 (*) 3.3 ( **) 5.0 3.3(*) 5.0
( **) (*) (*)
(*)
ns
tPZL tPZH
Out put En ableT ime
ns
tPLZ tPHZ tw ts th fMAX tOSLH tOSHL
Out put D isable T im e Clock P u lse W idth HIG H o r LO W Setu p T ime D to CK HIG H o r LO W Hold Ti me D to C K HIG H o r LO W Max im um C lock Freq uency Out put to Ou tp ut Sk ew Tim e (n ote 1 )
ns ns ns ns M Hz ns
3.3 ( **) 5.0 3.3 5.0( **) 3.3 ( **) 5.0 3.3 5.0
(*) ( **) (*) (*)
(*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5V ± 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm- tpLHn|, tsoHL = |tpHLm - tpHLn|
CAPACITIVE CHARACTERISTICS
S ym b o l P ar amet e r T est Co n d i t i o n s
o
V al u e TA = 25 C M in. T yp . 4 6 32 M ax. 10 - 40 t o 85 C Mi n. M ax. 10
o
Unit
CIN C OUT C PD
Input Capacita nce Out put C apacit ance Power D is sipat ion Capacit ance (n ote 1)
pF pF pF
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD · VCC · fIN + ICC/8 (per Flip-Flop)
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74VHC374
DYNAMIC SWITCHING CHARACTERISTICS
S ym b o l P ar amet e r T est Co n d i t i o n s V CC ( V) VOLP VOLV VIH D VILD Dynam ic Low V oltag e Quiet O utput ( note 1, 2) Dynam ic High Vo lt age Input (note 1 , 3) Dynam ic Low V oltag e Input (note 1 , 3) 5.0 -0.9 5.0 5.0 C L = 50 pF 3.5 1.5 M in. T yp . 0.6 -0.6 V V al u e T A = 2 5 oC M ax. 0.9 - 40 t o 85 o C Mi n. M ax. Unit
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n -1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
TEST CIRCUIT
T E ST t PLH, tPHL t PZL, tPL Z t PZH, tPHZ
CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1K or equivalent RT = ZOUT of pulse generator (typically 50)
SW I T C H Open VCC GND
5/10
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