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Part: 74LVC125PW
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Datasheet: Download 74LVC125PW datasheet File size : 291 kB
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INTEGRATED CIRCUITS
74LVC125 Quad buffer/line driver; 3-State
Product specification Supersedes data of February 1996 IC24 Data Handbook 1997 Mar 18
Philips Semiconductors
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-State
74LVC125
FEATURES
· Wide supply voltage range of 1.2 to 3.6 V · In accordance with JEDEC standard no. 8-1A · Inputs accept voltages up to 5.5 V · CMOS lower power consumption · Direct interface with TTL levels · Output drive capability 50 W transmission lines at 85°C
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns SYMBOL tPHL/tPLH CI CP D PARAMETER Propagation delay nA to nY Input capacitance Power dissipation capacitance per buffer
DESCRIPTION
The 74LVC125 is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC125 consists of four non-inverting buffers/line drivers with 3-State outputs. The 3-State outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high impedance OFF-state.
CONDITIONS CL = 15 pF; VCC = 3.3 V Notes 1 and 2
TYPICAL 3.5 5.0 22
UNIT ns pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74LVC125 D 74LVC125 DB 74LVC125 PW NORTH AMERICA 74LVC125 D 74LVC125 DB 74LVC125PW DH PKG. DWG. # SOT108-1 SOT337-1 SOT402-1
PIN CONFIGURATION
1OE 1A 1Y 2OE 2A 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4OE 4A 4Y 3OE 3A 3Y
LOGIC SYMBOL
2 1A 1Y 3
1 5
1OE 2A 2Y 6
4 9
2OE 3A 3Y 8
10
3OE 4A 4Y 11
SV00455
12
PIN DESCRIPTION
PIN NUMBER 1, 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 SYMBOL 1OE 4OE 1A 4A 1Y 4Y GND VCC NAME AND FUNCTION Data enable inputs (active LOW) Data inputs Data Outputs Ground (0 V) Positive supply voltage
13
4OE
SV00456
1997 Mar 18
2
8531951 17865
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-State
74LVC125
FUNCTION TABLE
INPUTS nOE L L H NOTES: H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state nA L H X OUTPUT nY L H Z
LOGIC SYMBOL (IEEE/IEC)
2 1 3 1 EN1 5 6 4 9 8 10 12 11 13
SV00457
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VCC VI VI/O VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range DC input voltage range for I/Os DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS LIMITS MIN 2.7 1.2 0 0 0 40 0 0 MAX 3.6 3.6 5.5 VCC VCC +85 20 10 UNIT V V V V V °C ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI VI/O IOK VOUT IOUT IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC input voltage range for I/Os DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VO uVCC or VO t 0 Note 2 VO = 0 to VCC VI t 0 Note 2 CONDITIONS RATING 0.5 to +6.5 50 0.5 to +5.5 0.5 to VCC +0.5 "50 0.5 to VCC +0.5 "50 "100 60 to +150 500 500 UNIT V mA V V mA V mA mA °C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1997 Mar 18
3
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-State
74LVC125
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOH HIGH level output voltage level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 12mA VCC = 3.0V; VI = VIH or VIL; IO = 24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IIHZ/IILZ IOZ ICC ICC Input leakage current leakage current Input current for common I/O pins 3-State output OFF-state current Quiescent supply current Additional quiescent supply current per input pin VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V or GND VCC = 3.6V; VI = VCC or GND VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC 0.6V; IO = 0 Not for I/O pins for I/O pins "0.1 "0.1 0.1 0.1 5 GND VCC*0.5 VCC*0.2 VCC*0.6 VCC*1.0 0.40 0.20 0.55 "5 "15 "10 20 500 µA µA µA µA µA V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C.
1997 Mar 18
4
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-State
74LVC125
AC CHARACTERISTICS
GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500W; Tamb = 40_C to +85_C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V MIN tPHL tPLH tPZH tPZL tPHZ tPLZ Propagation delay nA to nY 3-state output enable time nOE to nY 3-state output disable time nOE to nY Figure 1, 3 Figure 2, 3 Figure 2, 3 TYP1 3.5 3.8 3.3 MAX 6.5 7.0 5.5 MIN VCC = 2.7V TYP 3.9 4.4 4.0 MAX 7.0 8.0 6.5 VCC = 1.2V TYP ns ns ns UNIT
NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25°C.
AC WAVEFORMS
VM = 1.5 V at VCC w 2.7 V VM = 0.5 × VCC at VCC < 2.7 V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC 2.7 V; VX = VOL + 0.1 × VCC at VCC < 2.7 V; VY = VOH 0.3 V at VCC 2.7 V; VY = VOH 0.1 × VCC at VCC < 2.7 V.
Vl nA INPUT GND t PHL V OH nY OUTPUT V OL VM t PLH VM
TEST CIRCUIT
VCC S1 2 < VC C Open GND
PULSE GENERATOR
VI D.U.T. RT
VO
500
CL
50pF
500
Test VCC t 2.7V 2.7V 3.6V VI VCC 2.7V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2 < VCC GND
SY00003
Figure 3. Load circuitry for switching times.
SV00459
Figure 1. Input (nA) to output (nY) propagation delays.
VI nOE Input GND tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM outputs disabled outputs enabled tPZL VM VX tPZH VM
SV00458
Figure 2. 3-State enable and disable times.
1997 Mar 18
5
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