Details, datasheet, quote on part number: LMX2595RHAT
PartLMX2595RHAT
CategorySemiconductors => Clock and Timing => RF PLLs and Synthesizers
Part familyLMX2595 10 MHz - 19 GHz Wideband RF Synthesizer with Phase Synchronization and JESD204B support
TitlePhase Locked Loops - PLL 10 MHz - 19 GHz Wideband RF Synthesizer with Phase Synchronization and JESD204B support 40-VQFN -40 to 85
Description10 MHz - 19 GHz Wideband RF Synthesizer with Phase Synchronization and JESD204B support 40-VQFN -40 to 85
CompanyTexas Instruments Inc.
StatusACTIVE
ROHSY
SampleYes
DatasheetDownload LMX2595RHAT datasheet
Specifications 
TypeRF Synthesizer
Number of Circuits1
Maximum Input Frequency1400 MHz
Minimum Input Frequency5 MHz
Output Frequency Range10 MHz to 19 GHz
Supply Voltage - Max3.45 V
Supply Voltage - Min3.15 V
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT
Package/CaseVQFN-40
PackagingCut Tape, eel, Reel
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
40RHAVQFNS-PQFP-N250SMALL T&RLMX2595 66.9.5
Evaluation Kits
LMX2595EVM: 19GHz Wideband RF Synthesizer With Phase Synchronization and JESD204B Evaluation Module

Others parts numbering
LMX2595RHAR

 

Features, Applications

LMX2595 19-GHz Wideband PLLatinumTM RF Synthesizer With Phase Synchronization and JESD204B Support

The LMX2595 high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 19 GHz. An integrated doubler is used for frequencies above 15 GHz. The high performance PLL with figure of merit of 236 dBc/Hz and highphase detector frequency can attain very low in-band noise and integrated jitter. The high speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs. The LMX2595 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize to 2 segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 s. The LMX2595 adds support for generating or repeating SYSREF (compliant to JESD204B standard) making it an ideal low-noise clock source for high-speed data converters. Fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces. The output drivers within LMX2595 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs. Device Information(1)

PART NUMBER LMX2595 PACKAGE VQFN (40) BODY SIZE (NOM) 6.00 mm

to 19-GHz Output Frequency 110 dBc/Hz Phase Noise at 100-kHz Offset With 15-GHz Carrier 45-fs rms Jitter at 7.5 GHz to 100 MHz) Programmable Output Power PLL Key Specifications Figure of Merit: 236 dBc/Hz Normalized 1/f Noise: 129 dBc/Hz High Phase Detector Frequency 400-MHz Integer Mode 300-MHz Fractional Mode 32-bit Fractional-N Divider Remove Integer Boundary Spurs With Programmable Input Multiplier Synchronization of Output Phase Across Multiple Devices Support for SYSREF With 9-ps Resolution Programmable Delay Frequency Ramp and Chirp Generation Ability for FMCW Applications < 20-s VCO Calibration Speed 3.3-V Single Power Supply Operation

5G and mm-Wave Wireless Infrastructure Test and Measurement Equipment Radar MIMO Phased Array Antennas and Beam Forming High-Speed Data Converter Clocking (Supports JESD204B)

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Loop Filter CPout OSCinP Input signal OSCinM Sigma-Delta Modulator CSB SCK SDI MUXout Serial Interface Control

Phase Detector OSCin Douber Pre-R Divider Multiplier Post-R Divider
Vtune Charge Pump 2X Channel Divider RFoutBM Vcc RFoutBP SYSREF

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Features.................................................................. Applications........................................................... Description............................................................. Revision History..................................................... Pin Configuration and Functions......................... Specifications.........................................................

Absolute Maximum Ratings...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information.................................................. 5 Electrical Characteristics........................................... 6 Timing Requirements................................................ 9 Typical Characteristics............................................ 11 Overview................................................................. Functional Block Diagram....................................... Feature Description................................................. Device Functional Modes........................................

Device Support...................................................... Documentation Support........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks........................................................... Electrostatic Discharge Caution............................ Glossary................................................................

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2017) to Revision A Page

Added Clarified that output power assumes that load is matched and losses are de-embedded....................................... 6 Changed Swapped SDI and SCK in diagram.................................................................................................................... 10 Added Adding INPIN_IGNORE, INPIN_LVL, and INPIN_HYST.......................................................................................... 40 Changed Removed RAMP0_FL from register map............................................................................................................ 41 Changed OUT_ISEL to OUTI_SET..................................................................................................................... 47 Added Section for input register descriptions.......................................................................................................... 47 Changed Fixed TYPO table to match main register map..................................................................................................... 49 Changed Corrected RAMP_BURST_TRIG description to match other place in datasheet................................................ 52 Changed Removed duplicate error R101[2].................................................................................................................... 53 Changed RAMP1_INC changed from RAMP1................................................................................................. 53 Changed Clarified that the delay was in state machine cycles.......................................................................................... 53 Changed Fixed Pin Names in Schematic............................................................................................................................ 57

Submit Documentation Feedback Product Folder Links: LMX2595
CE GND VbiasVCO GND SYNC GND VccDIG OSCinP OSCinM VregIN

 

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