Details, datasheet, quote on part number: R5F562N8BDFB#V0
Title32-bit Microcontrollers - MCU RX62N 512K/96K,QFP144,2.7 3.6V
DatasheetDownload R5F562N8BDFB#V0 datasheet
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Features, Applications

100 MHz 32-bit RX MCU with FPU, 165 DMIPS, to 512-Kbyte Flash, Ethernet, USB 2.0 Full-Speed Host/Function/OTG, CAN, 12-bit ADC, TFT-LCD, RTC, to 14 communication channels


Delivers 165 DMIPS at a maximum operating frequency of 100 MHz Single Precision 32-bit IEEE-754 Floating Point Accumulator: to 64-bit result, one instruction Mult/Divide Unit, × 32 Multiply in one CPU clock for multiple instructions Interrupt response in as few as 5 CPU clock cycles CISC-Harvard Architecture with 5-stage pipeline Variable length instructions, ultra compact code Supports the Memory Protection Unit (MPU) Background JTAG debug plus high-speed trace

USB 2.0 Full-Speed interfaces with PHY (2 ch) Supports Host/Function/OTG 10 endpoints for types: Control, Interrupt, Bulk, Isochronous Ethernet MAC 10/100 Mbps, Half or Full Duplex Supported. (1 ch) Dedicated DMA with 2-Kbyte transmit and receive FIFOs. RMII or MII interface to external PHY CAN ISO11898-1, supports 32 mailboxes (1 ch) SCI channels: Asynchronous, clock sync, smartcard, and 9bit modes (6 ch) I2C interfaces 1 M bps, SMBus support (2 ch) RSPI (2 ch)

to 3.6V operation from a single supply 480 ľA/MHz Run Mode with all peripherals on Deep Software Standby Mode with RTC Four low power modes

100 MHz operation, 10 nsec read cycle No wait states for read at full CPU speed 384K, 512K Byte size options For Instructions or Operands Programming from USB, SCI, JTAG, user code

Eight CS areas × 16 Mbytes) 128-Mbyte SDRAM area 8-/16-/32-bit bus space selectable for each area
to 32K Bytes with 30K Erase Cycles Background Erase/Program does not stall CPU
TFT-LCD up to WQVGA resolution to 20 Extended Function Timers

16-bit MTU2 Input capture, Output Compare, PWM output, phase count mode (12 ch) 8-bit TMR (4 ch) 16-bit CMT (4 ch)

or 96K Byte size options For Operands or Instructions Back-up retention in Deep Software Standby Mode

Four fully programmable internal DMA channels Two EXDMA channels for external-to-external transfers Data Transfer Controller (DTC)

× 8 ch. unit with single sample/hold circuit 4 ch units each with a sample/hold circuit AD-converted value addition mode (12-bit A/D converter)

Power-On Reset (POR) monitor/generator Low Voltage Detect (LVD) with precision setting

External crystal, 8 MHz to 14 MHz to Internal PLL source to system, USB, and Ethernet Internal 125 kHz LOCO for IWDT External crystal, 32 kHz for RTC

Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products. Table 1.1

RAM Data flash MCU operating modes Clock generation circuit

Maximum operating frequency: 100 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 Floating-point instructions: 8 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 64 bits On-chip divider: bits Barrel shifter: 32 bits Memory-protection unit (MPU) Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard ROM capacity: 512 Kbytes (max.) Two on-board programming modes Boot mode (The user MAT is programmable via the SCI and USB.) User program mode Parallel programmer mode (for off-board programming)

RAM capacity: 96 Kbytes (max.) Data flash capacity: 32 Kbytes

Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode (software switching) Two circuits: Main clock oscillator and subclock oscillator Internal oscillator: Low-speed on-chip oscillator Structure of a PLL frequency synthesizer and frequency divider for selectable operating frequency Oscillation stoppage detection Independent frequency-division and multiplication settings for the system clock (ICLK), peripheral module clock (PCLK), and external bus clock (BCLK) The CPU and other bus masters run in synchronization with the system clock (ICLK): to 100 MHz Peripheral modules run in synchronization with the peripheral module clock (PCLK): to 50 MHz Devices connected to the external bus run in synchronization with the external bus clock (BCLK pin): 50 MHz*1 Pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent watchdog timer reset, and deep software standby reset When the voltage on VCC falls below the voltage detection level (Vdet), an internal reset or internal interrupt is generated. Module stop function Four low power consumption modes Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode

Reset Voltage detection circuit Low power consumption Low power consumption facilities

Peripheral function interrupts: 146 sources External interrupts: 16 (pins to IRQ15) Non-maskable interrupts: 3 (the NMI pin, oscillation stop detection interrupt, and voltagemonitoring interrupt) Sixteen levels specifiable for the order of priority Two breakpoint channels Address breaks in fetch cycles are specifiable (enabling ROM correction) The external address space can be divided into nine areas to CS7, SDCS), each with independent control of access settings. Capacity of each area: 16 Mbytes CS7), 128 Mbytes (SDCS) A chip-select signal to CS7#, SDCS#) can be output for each area. Each area is specifiable or 32-bit bus space (however, only 176-pin versions support 32-bit bus spaces). The data arrangement in each area is selectable as little or big endian (only for data). SDRAM interface connectable Bus format: Separate buses Wait control Write buffer facility 4 channels Three transfer modes: Normal transfer, repeat transfer, and block transfer Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral functions 2 channels Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster transfer Single-address transfer enabled with the EDACK signal Capable of direct data transfer to TFT LCD panels Activation sources: Software trigger, external DMA transfer requests (EDREQ), and interrupt requests from peripheral functions Three transfer modes: Normal transfer, repeat transfer, and block transfer Activation sources: Software trigger, external interrupts and interrupt requests from peripheral functions I/O ports for the LQFP/100-pin LQFP/85-pin TFLGA I/O pins: 126/103/103/72/58 Input pins: 2/2/2/2/2 Pull-up resistors: 56/44/44/40/28 Open-drain outputs: 35/33/33/27/23 5-V tolerance: 11/11/11/7/6 (16 bits x 6 channels) x 2 units Time bases for the 12 16-bit timer channels can be provided via to 32 pulse-input/ output lines and six pulse-input lines Select from among eight counter-input clock signals for each channel PCLK/16, PCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5, for which only four signals are available. Input capture function 21 output compare/input capture registers Pulse output mode Complementary PWM output mode Reset synchronous PWM mode Phase-counting mode Generation of triggers for A/D converter conversion Controls the high-impedance state of the MTU's waveform output pins

User break controller (as an optional function) External bus extension
Data transfer controller I/O ports Programmable I/O ports


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