Details, datasheet, quote on part number: ADF4169CCPZ
PartADF4169CCPZ
Category
TitleIC PLL FREQ SYNTHESIZER 24LFCSP
Description

ADI’s ADF4169 is a 13.5 GHz, fractional-N frequency synthesizer that is complete with modulation and both fast and slow waveform generation capability. The part uses a 25-bit fixed modulus, allowing sub-hertz frequency resolution. This synthesizer can be used to implement frequency shift keying (FSK) and phase shift keying (PSK) modulation. Frequency sweep modes are also available to generate various waveforms in the frequency domain, for example, sawtooth, and triangular waveforms. The device comes in a 24-pin LFCSP package and has a temperature range of -40°C to +125°C. The ADF4169 is ideal for communication systems, test equipment, and FMCW radar.



CompanyAnalog Devices
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Features, Applications
Direct Modulation/Fast Waveform Generating, 13.5 GHz, Fractional-N Frequency Synthesizer
FEATURES

RF bandwidth to 13.5 GHz High and low speed FMCW ramp generation 25-bit fixed modulus allows subhertz frequency resolution PFD frequencies to 130 MHz Normalized phase noise floor of -224 dBc/Hz FSK and PSK functions Sawtooth and triangular waveform generation Ramp superimposed with FSK Ramp with 2 different sweep rates Ramp delay, frequency readback, and interrupt functions Programmable phase control 3.45 V analog power supply 2 V digital power supply Programmable charge pump currents 3-wire serial interface Digital lock detect ESD performance: 3000 V HBM, 1000 V CDM Qualified for automotive applications

The a 13.5 GHz, fractional-N frequency synthesizer with modulation and both fast and slow waveform generation capability. The device uses a 25-bit fixed modulus, allowing subhertz frequency resolution. The ADF4169 consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. The --based fractional interpolator allows programmable fractional-N division. The INT and FRAC registers define an overall N divider N = INT + (FRAC/225). The ADF4169 can be used to implement frequency shift keying (FSK) and phase shift keying (PSK) modulation. Frequency sweep modes are also available to generate various waveforms in the frequency domain, for example, sawtooth waveforms and triangular waveforms. Sweeps can be set to run automatically or with each step manually triggered by an external pulse. The ADF4169 features cycle slip reduction (CSR) circuitry, which enables faster lock times without the need for modifications to the loop filter. Control of all on-chip registers is via a simple 3-wire interface. The ADF4169 operates with an analog power supply in the range 3.45 V and a digital power supply in the range 2 V. The device can be powered down when not in use.

APPLICATIONS
FMCW radars Communications test equipment Communications infrastructure
REFERENCE REFIN 2 DOUBLER 5-BIT R COUNTER 2 DIVIDER + PHASE FREQUENCY DETECTOR SW2

DGND OUTPUT MUX SERIAL DATA OUTPUT DVDD DIVIDER/2 N COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR FRACTION VALUE MODULUS 225 VALUE INTEGER VALUE + LOCK DETECT

Rev. 0 Document Feedback One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Features.............................................................................................. 1 Applications....................................................................................... 1 General Description......................................................................... 1 Functional Block Diagram.............................................................. 1 Revision History............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications.................................................................. 4 Absolute Maximum Ratings............................................................ 6 Thermal Resistance...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics............................................. 8 Theory of Operation...................................................................... 10 Reference Input Section............................................................. 10 RF Input Stage............................................................................. 10 RF INT Divider........................................................................... 10 25-Bit Fixed Modulus................................................................ 10 INT, FRAC, and R Counter Relationship................................ 10 R Counter.................................................................................... 10 Phase Frequency Detector and Charge Pump........................... 11 MUXOUT and Lock Detect...................................................... 11 Input Shift Register..................................................................... 11 Program Modes.......................................................................... 11 Register Maps.................................................................................. 12 FRAC/INT Register (R0) Map.................................................. 14 LSB FRAC Register (R1) Map................................................... 15 R Divider Register (R2) Map.................................................... 16 Function Register (R3) Map...................................................... 18 Clock Register (R4) Map........................................................... 20 Deviation Register (R5) Map.................................................... 22

Step Register (R6) Map.............................................................. 23 Delay Register (R7) Map........................................................... 24 Applications Information.............................................................. 25 Initialization Sequence.............................................................. 25 RF Synthesizer Worked Example............................................. 25 Reference Doubler...................................................................... 25 Cycle Slip Reduction for Faster Lock Times........................... 25 Modulation.................................................................................. 26 Waveform Generation............................................................... 26 Waveform Deviations and Timing........................................... 27 Single Ramp Burst...................................................................... 27 Single Triangular Burst.............................................................. 27 Single Sawtooth Burst................................................................ 27 Continuous Sawtooth Ramp..................................................... 27 Continuous Triangular Ramp................................................... 27 FMCW Radar Ramp Settings Worked Example...................... 27 Activating the Ramp.................................................................. 28 Other Waveforms....................................................................... 28 Ramp Complete Signal to MUXOUT..................................... 31 External Control of Ramp Steps............................................... 31 Interrupt Modes and Frequency Readback............................ 31 Fast Lock Mode.......................................................................... 33 Spur Mechanisms....................................................................... 33 Filter Design Using ADIsimPLL............................................... 34 PCB Design Guidelines for the Chip Scale Package.............. 34 Application of the ADF4169 in FMCW Radar...................... 35 Outline Dimensions....................................................................... 36 Ordering Guide.......................................................................... 36 Automotive Products................................................................. 36

AVDD 3.45 V, DVDD = SDVDD 1.9 V, AGND = DGND = SDGND = CPGND 0 V, fPFD = 130 MHz, TA = TMIN to TMAX, dBm referred 50 , unless otherwise noted. Table 1.

Parameter1 RF CHARACTERISTICS RF Input Frequency, RFIN Min 0.5 Typ Max 13.5 Unit GHz Test Conditions/Comments -10 dBm minimum to 0 dBm maximum; for lower frequencies, ensure a slew rate 400 V/s For higher frequencies, use 8/9 prescaler -5 dBm minimum to +9 dBm maximum biased at 1.9/2 (ac coupling ensures 1.9/2 bias); for frequencies < 10 MHz, use a dccoupled, CMOS-compatible square wave with a slew rate > 25 V/s Bit DB20 in Register R2 set to 1

Prescaler Output Frequency REFERENCE CHARACTERISTICS REFIN Input Frequency

Reference Doubler Enabled REFIN Input Capacitance REFIN Input Current PHASE FREQUENCY DETECTOR, PFD Phase Detector Frequency, fPFD2 CHARGE PUMP (CP) ICP Sink/Source Current High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Sink and Source Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output Voltage High, VOH Output Voltage Low, VOL Output High Current, IOH POWER SUPPLIES AVDD DVDD, SDVDD VP AIDD DIDD IP Power-Down Mode

Programmable RSET 5.1 k RSET 5.1 k Sink and source current V < VCP V < VCP 0.5 V VCP = VP/2

Supply current drawn by AVDD; fPFD = 130 MHz Supply current drawn by DVDD; fPFD = 130 MHz Supply current drawn by VP; fPFD = 130 MHz


 

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