Details, datasheet, quote on part number: IS43LD16640C-25BLI
PartIS43LD16640C-25BLI
Category
TitleIC SDRAM 1GBIT 400MHZ 134TFBGA
Description

ISSI's IS43LD16640C/32320C are 1 Gbit CMOS LPDDR2 DRAMs. The devices are organized as eight banks of 8 Meg words of 16-bits or 4 Meg words of 32-bits. These products use a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 4N pre-fetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. They offer fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 4N bits pre-fetched to achieve very high bandwidth.



CompanyIntegra Technologies
DatasheetDownload IS43LD16640C-25BLI datasheet
  
IS43LD16640C-25BLI photo

Others parts numbering
IS43LD32320C-25BLI
IS43LD16640C-25BLI-TR
IS43LD32320C-25BLI-TR

 

Features, Applications
FEATURES

Low-voltage Core and I/O Power Supplies = 1.14-1.30V, VDDCA/VDDQ = 1.70-1.95V High Speed Un-terminated Logic(HSUL_12) I/O Interface Clock Frequency Range to 533MHz (data rate range to 1066Mbps per I/O) Four-bit Pre-fetch DDR Architecture Multiplexed, double data rate, command/address inputs Eight internal banks for concurrent operation Bidirectional/differential data strobe per byte of data (DQS/DQS#) Programmable Read/Write latencies(RL/WL) and burst 16) ZQ Calibration On-chip temperature sensor to control self refresh rate Partial ­array self refresh(PASR) Deep power-down mode(DPD) Operation Temperature

description

The is 1Gbit CMOS LPDDR2 DRAM. The device is organized as 8 banks of 8Meg words or 4Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 4n bits prefetched to achieve very high bandwidth.

Parameter Row Addresses Column Addresses Bank Addresses Refresh Count BA0-BA2 4096
Speed Grade -25 -3 Data Rate (Mb/s) 800 667 Write Read tRCD/ Latency tRP2 Typical
OPTIONS

Note: 1. Other clock frequencies/data rates supported; please refer to AC timing tables. 2. Please contact ISSI for fast tRCD/tRP

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances



 

Some Part number from the same manufacture Integra Technologies
IS43LD32320C-25BLI

ISSI's IS43LD16640C/32320C are 1 Gbit CMOS LPDDR2 DRAMs. The devices are organized as eight banks of 8 Meg words of 16-bits or 4 Meg words of 32-bits. These products use a double-data-rate architecture

IS43LD16640C-25BLI-TR
IS43LD32320C-25BLI-TR
 
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