|Title||IC MCU 32BIT 128KB FLASH 48LFQFP|
|Company||America Semiconductor, LLC|
|Datasheet||Download R7FS124773A01CFLAA0 datasheet
|Others parts numbering|
|R7FS124773A01CFMAA0: IC MCU 32BIT 128KB FLASH 64LFQFP|
|R7FS124773A01CNBAC0: IC MCU 32BIT 128KB FLASH 64HWQFN|
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|R7FS124773A01CNEAC0: IC MCU 32BIT 128KB FLASH 48HWQFN|
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Ultra-low power 32-MHz ARM® Cortex®-M0+ microcontroller, to 128-KB code flash memory, 16-KB SRAM, Capacitive Touch Sensing Unit, 14-bit A/D Converter, 12-bit D/A Converter, security and safety features.
ARMv6-M architecture Maximum operating frequency: 32 MHz Debug and Trace: DWT, BPU, CoreSightTM MTB-M0+ CoreSight Debug Port: SW-DP to 128-KB code flash memory 4-KB data flash memory (up to 100,000 erase/write cycles) to 16-KB SRAM 128-bit unique ID
Low-power modes RealTime Clock (RTC) Event Link Controller (ELC) Data Transfer Controller (DTC) Key Interrupt Function (KINT) Power-on reset Low Voltage Detection with voltage settings
AES128/256 True Random Number Generator (TRNG) Capacitive Touch Sensing Unit (CTSU) Main clock oscillator (MOSC) to 20 MHz when VCC to 8 MHz when VCC to 4 MHz when VCC 5.5 V) Sub-clock oscillator (SOSC) (32.768 kHz) High-speed on-chip oscillator (HOCO) MHz when VCC 32, 48 MHz when VCC (24, 32 MHz when VCC 5.5 V) Middle-speed on-chip oscillator (MOCO) (8 MHz) Low-speed on-chip oscillator (LOCO) (32.768 kHz) Independent watchdog timer OCO (15 kHz) Clock trim function for HOCO/MOCO/LOCO Clock out support to 51 input/output pins to 3 CMOS input to 48 CMOS input/output 6 5-V tolerant input/output (when VCC to 16 pins high current (20 mA) VCC: 5.5 V
USB 2.0 Full-Speed Module (USBFS) - On-chip transceiver with voltage regulator - Compliant with USB Battery Charging Specification 1.2 Serial Communications Interface (SCI) 3 - UART - Simple IIC - Simple SPI Serial Peripheral Interface (SPI) 2 I2C bus interface (IIC) × 2 CAN module (CAN) 14-Bit A/D Converter (ADC14) 12-Bit D/A Converter (DAC12) Low-Power Analog Comparator (ACMPLP) × 2 Temperature Sensor (TSN) General PWM Timer 32-Bit (GPT32) General PWM Timer × 6 Asynchronous General-Purpose Timer (AGT) × 2 Watchdog Timer (WDT) SRAM Parity Error Check Flash Area Protection ADC self-diagnosis function Clock Frequency Accuracy Measurement Circuit (CAC) Cyclic Redundancy Check (CRC) Calculator Data Operation Circuit (DOC) Port Output Enable for GPT (POEG) Independent Watchdog Timer (IWDT) GPIO Readback Level Detection Register Write Protection Main Oscillator Stop DetectionHuman Machine Interface (HMI) Multiple Clock Sources
- 36-pin LGA × 4 mm, 0.5 mm pitch) - 64-pin LQFP × 10 mm, 0.5 mm pitch) - 48-pin LQFP × 7 mm, 0.5 mm pitch) - 64-pin QFN × 8 mm, 0.4 mm pitch) - 48-pin QFN × 7 mm, 0.5 mm pitch) - 40-pin QFN × 6 mm, 0.5 mm pitch)
The S124 MCU comprises multiple series of software- and pin-compatible ARM-based 32-bit MCUs that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. Based on the energy-efficient ARM® Cortex®-M0+ 32-bit core, this MCU is particularly well suited for cost-sensitive and low-power applications. The MCU in this series feature: 128 KB code flash memory 16-KB SRAM Capacitive Touch Sensing Unit (CTSU) 14-bit ADC 12-bit DAC Security features.Feature
Functional description Maximum operating frequency: to 32 MHz ARM Cortex-M0+: - Revision: - ARMv6-M architecture profile - Single-cycle integer multiplier. SysTick timer - Driven by LOCO clock.
Functional description Maximum 128 KB code flash memory. See section 37, Flash Memory in User's Manual. 4 KB data flash memory. See section 37, Flash Memory in User's Manual. The option-setting memory determines the state of the MCU after a reset. See section 6, Option-Setting Memory and Information Memory in User's Manual. The MCU has an on-chip high-speed SRAM with even parity bit. See section 36, SRAM in User's Manual.Code flash memory Data flash memory Option-Setting Memory SRAM
Functional description Two operating modes: Single-chip mode SCI boot mode. See section 3, Operating Modes in User's Manual. The MCU has 9 types of resets: RES pin reset Power-on reset Independent watchdog timer reset Watchdog timer reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset SRAM parity error reset Software reset. See section 5, Resets in User's Manual.
Functional description The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin and the detection level can be selected using a software program. See section 7, Low Voltage Detection (LVD) in User's Manual. Main clock oscillator (MOSC) Sub-clock oscillator (SOSC) High-speed on-chip oscillator (HOCO) Middle-speed on-chip oscillator (MOCO) Low-speed on-chip oscillator (LOCO) Independent Watchdog Timer on-chip oscillator Clock out support. See section 8, Clock Generation Circuit in User's Manual. The clock frequency accuracy measurement circuit (CAC) is used to check the system clock frequency with a reference clock signal by counting the number of pulses of the system clock to be measured. The reference clock can be provided externally through a CACREF pin or internally from various on-chip oscillators. Event signals can be generated when the clock does not match or measurement ends. This feature is particularly useful in implementing a fail-safe mechanism for home and industrial automation applications. See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User's Manual. The MCU has several functions for reducing power consumption, such as setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. See section 10, Low Power Modes in User's Manual. The Register Write Protection function protects important registers from being overwritten due to software errors. See section 11, Register Write Protection in User's Manual. The Watchdog Timer (WDT) a 14-bit down-counter. It can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The refresh-permitted period can be set to refresh the counter and used as the condition to detect when the system runs out of control. See section 22, Watchdog Timer (WDT) in User's Manual. The Independent Watchdog Timer (IWDT) consists a 14-bit down-counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail safe mechanism when the system runs out of control. The watchdog timer can be triggered automatically on reset, underflow, or refresh error, by a refresh of the count value in the registers. See section 23, Independent Watchdog Timer (IWDT) in User's Manual.Clock Frequency Accuracy Measurement Circuit (CAC)
Register Write Protection Watchdog Timer (WDT)
Functional description The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC module. The ICU also controls NMI interrupts. See section 12, Interrupt Controller Unit (ICU) in User's Manual.
Functional description The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral modules as event signals to connect them to different modules, enabling direct interaction between the modules without CPU intervention. See section 15, Event Link Controller (ELC) in User's Manual.
Functional description The MCU incorporates a Data Transfer Controller (DTC) that performs data transfers when activated by an interrupt request. See section 14, Data Transfer Controller (DTC) in User's Manual.
|Some Part number from the same manufacture America Semiconductor, LLC|