Details, datasheet, quote on part number: LPC54114J256BD64QL
TitleARM Microcontrollers - MCU BL Microcontrollers

NXP LPC5411x ARM® Cortex®-M4 Microcontrollers (MCU) are low power consumption MCUs with enhanced debug features and a high level of support block integration. The LPC5411x series include devices with up to 192KB of on-chip SRAM and up to 256KB on-chip flash. The LPC54114 includes an ARM Cortex-M0+ coprocessor. The MCUs address a variety of always-on applications with several interfaces and smart peripherals. These interfaces and peripherals include a Digital Microphone Subsystem, crystal-less FS USB and FlexComm interface.

CompanyNXP Semiconductors
DatasheetDownload LPC54114J256BD64QL datasheet
LPC54114J256BD64QL photo

Others parts numbering
OM13089,598: Development Boards & Kits - ARM LPCXpresso54114 board


Features, Applications

32-bit ARM Cortex-M4/M0+ MCU; 192 KB SRAM; 256 KB flash, Crystal-less USB operation, DMIC subsystem, Flexcomm Interface, 32-bit counter/ timers, SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC, Temperature sensor

The LPC5411x are ARM Cortex-M4 based microcontrollers for embedded applications. These devices include an ARM Cortex-M0+ coprocessor, KB of on-chip SRAM, 256 KB on-chip flash, full-speed USB device interface with Crystal-less operation, a DMIC subsystem with PDM microphone interface and I2S, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), eight flexible serial communication peripherals (each of which can be a USART, SPI, or I2C interface), and one 12-bit 5.0 Msamples/sec ADC, and a temperature sensor. The ARM a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core. The ARM Cortex-M0+ coprocessor is an energy-efficient and easy-to-use 32-bit core which is code and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor offers to 100 MHz performance with a simple instruction set and reduced code size.

Dual processor cores: ARM Cortex-M4 and ARM Cortex-M0+. Both cores operate to a maximum frequency of 100 MHz. ARM Cortex-M4 core (version r0p1): ARM Cortex-M4 processor, running at a frequency to 100 MHz. Floating Point Unit (FPU) and Memory Protection Unit (MPU). ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input with a selection of sources. Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators, and four watch points. Includes Serial Wire Output for enhanced debug capabilities. System tick timer.

ARM Cortex-M0+ core ARM Cortex-M0+ processor, running at a frequency to 100 MHz (uses the same clock as Cortex-M4) with a single-cycle multiplier and a fast single-cycle I/O port. ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input with a selection of sources. Serial Wire Debug with four breakpoints and two watch points. System tick timer. On-chip memory: 256 KB on-chip flash program memory with flash accelerator and 256 byte page erase and write. 192 KB total SRAM consisting 160 KB contiguous main SRAM and an additional 32 KB SRAM on the I&D buses. ROM API support: Flash In-Application Programming (IAP) and In-System Programming (ISP). ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB is supported. Supports booting from valid user code in flash, USART, SPI, and I2C. Legacy, Single, and Dual image boot. Serial interfaces: Flexcomm Interface contains eight serial peripherals. Each can be selected by software be a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I2S if supported by that Flexcomm Interface. A variety of clocking options are available to each Flexcomm Interface and include a shared fractional baud-rate generator. I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I2C pads also support high speed mode (3.4 Mbit/s) as a slave. Crystal-less USB full-speed device interface. Digital peripherals: DMA controller with 20 channels and 20 programmable triggers, able to access all memories and DMA-capable peripherals. to 48 General-Purpose Input/Output (GPIO) pins. Most GPIOs have configurable pull-up/pull-down resistors, programmable open-drain mode, and input inverter. GPIO registers are located on the AHB for fast access. Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or both input edges. Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states. CRC engine.

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Analog peripherals: 12-bit ADC with 12 input channels and with multiple internal and external trigger inputs and sample rates to 5.0 MSamples/sec. The ADC supports two independent conversion sequences. Integrated temperature sensor connected to the ADC. DMIC subsystem including a dual-channel PDM microphone interface, flexible decimators, 16 entry FIFOs, optional DC locking, hardware voice activity detection, and the option to stream the processed output data to I2S. Timers: Five 32-bit standard general purpose timers/counters, four of which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests. The fifth timer does not have external pin connections and may be used for internal timing operations. One SCTimer/PWM with eight input and eight output functions (including capture and match). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports ten captures/matches, ten events, and ten states. 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power domain. A timer in the RTC can be used for wake-up from all low power modes including deep power-down, with 1 ms resolution. Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation up to four programmable, fixed rates. Windowed Watchdog Timer (WWDT). Clock generation: 12 MHz internal Free Running Oscillator (FRO). This oscillator provides a selectable 48 MHz or 96 MHz output, and a 12 MHz output (divided down from the selected higher frequency) that can be used as a system clock. The FRO is trimmed 1 % accuracy over the entire voltage and temperature range. External clock input for clock frequencies to 25 MHz. Watchdog oscillator (WDTOSC) with a frequency range of 6 kHz to 1.5 MHz. 32.768 kHz low-power RTC oscillator. System PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency external clock. May be run from the internal FRO 12 MHz output, the external clock input CLKIN, or the RTC oscillator. Clock output function with divider. Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal. Power control: Programmable PMU (Power Management Unit) to minimize power consumption and to match requirements at different performance levels. Reduced power modes: sleep, deep-sleep, and deep power-down. Wake-up from deep-sleep modes due to activity on the USART, SPI, and I2C peripherals when operating as slaves.


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