Details, datasheet, quote on part number: LMK03318RHST
CategorySemiconductors => Clock and Timing => Clock Generators => Ultra-Low Jitter <300fsec-RMS
Part familyLMK03318 Ultra-Low Jitter Clock Generator Family With Single PLL
DescriptionUltra-Low Jitter Clock Generator Family With Single PLL 48-WQFN -40 to 85
CompanyTexas Instruments Inc.
DatasheetDownload LMK03318RHST datasheet
Package GroupWQFN
VCC Out(V)3.3,2.5,1.8
Operating Temperature Range(C)-40 to 85
VCC Core(V)3.3
Approx. Price (US$)7.50 | 1ku
Number of Outputs8
ProgrammabilityEEPROM,I2C,Pin configuration
Output Frequency(Max)(MHz)1000
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
48RHSWQFNS-PQFP-N250SMALL T&RK03318A 77.75.5
Application notes
• Frequency Margining Using TI High-Performance Clock Generators (Rev. A)
Crystal oscillators and/or multiple output clock generators are critical in today’s high performance consumer, computing and communications systems. Deciding an optimal clock rate for the system can sometimes require several rounds of prototyping and val | Doc
• Clocking High Speed Serial Links with LMK033X8 (Rev. A)
This application report outlines the advantages of using ultra-high performance clock generators from Texas Instruments to generate system clocks needed for high-speed serial links. A methodology for deriving reference clock jitter requirements for high-sp | Doc
Evaluation Kits
LMK03318EVM: LMK03318EVM Ultra-Low-Jitter Clock Generator EVM with 1 PLL, 8 Differential Outputs, and 2 Inputs

Others parts numbering


Features, Applications

LMK03318 Ultra-Low-Noise Jitter Clock Generator Family with One PLL, Eight Outputs, Integrated EEPROM

Ultra-Low Noise, High Performance Jitter: 100-fs RMS Typical, FOUT > 100 MHz PSRR: 70 dBc, Robust Supply Noise Immunity Flexible Device Options to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs or Any Combination Pin Mode, I2C Mode, EEPROM Mode 71-Pin Selectable Pre-programmed Default Start-up Options Dual Inputs with Automatic or Manual Selection Crystal Input: to 52 MHz External Input: to 300 MHz Frequency Margining Options Fine frequency Margining Using Low-Cost Pullable Crystal Reference Glitchless Coarse Frequency Margining Using Output Dividers Other Features Supply: 3.3 V Core, 3.3 V Output Supply

Switches and Routers Network and Telecom Line Cards Servers and Storage Systems Wireless Base Station

The is an ultra-low-noise PLLatinumTM clock generator with one fractional-N frequency synthesizer with integrated VCO, flexible clock distribution/fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, thus reducing BOM cost and board area and improving reliability by replacing multiple oscillators and clock distribution devices. The ultra-low jitter reduces bit-error rate (BER) in high-speed serial links. Device Information(1)

(1) For all available packages, see the orderable addendum at the end of the data sheet.
Power Conditioning PLL Output Dividers 8 Output Buffers 8 Smart MUX

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

For the PLL, a differential/single-ended clock or crystal input can be selected as its reference clock. The selected reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input frequency. The VCO frequency can be tuned between 4.8 GHz and 5.4 GHz. The PLL offers the flexibility to select a predefined or user-defined loop bandwidth, depending on the needs of the application. The PLL has a post-divider that can be selected between divide-by or 8. All the output channels can select the divided-down VCO clock from the PLL as the source for the output divider to set the final output frequency. Some output channels can also independently select the reference input for the PLL as an alternative source to be bypassed to the corresponding output buffers. The 8-bit output dividers support a divide range to 256 (even or odd), output frequencies to 1 GHz, and output phase synchronization capability. All output pairs are ground-referenced CML drivers with programmable swing that can be interfaced to LVDS, LVPECL or CML receivers with AC coupling. All output pairs can also be independently configured as HCSL outputs 1.8-V LVCMOS outputs. The outputs offer lower power 1.8 V, higher performance and power supply noise immunity, and lower EMI compared to voltage-referenced driver designs (such as traditional LVDS and LVPECL drivers). Two additional 3.3-V LVCMOS outputs can be obtained via the STATUS pins. This is an optional feature in case of a need for 3.3-V LVCMOS outputs and device status signals are not needed. The device features self start-up from on-chip programmable EEPROM or pre-defined ROM memory, which offers multiple custom device modes selectable via pin control eliminating the need for serial programming. The device registers and on-chip EEPROM settings are fully programmable via the I2C-compatible serial interface. The device slave address is programmable in EEPROM and LSBs can be set with a 3-state pin. The device provides two frequency margining options with glitch-free operation to support system design verification tests (DVT), such as standard compliance and system timing margin testing. Fine frequency margining (in ppm) can be supported by using a low-cost pullable crystal on the internal crystal oscillator (XO), and selecting this input as the reference to the PLL synthesizer. The frequency margining range is determined by the crystal's trim sensitivity and the on-chip varactor range. XO frequency margining can be controlled through pin or I2C control for ease-of use and high flexibility. Coarse frequency margining (in is available on any output channel by changing the output divide value via I2C interface, which synchronously stops and restarts the output clock to prevent a glitch or runt pulse when the divider is changed. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from 5% supply and output blocks operate from 5% supply.

Table 1. LVPECL Output Jitter over Different Integration Bandwidths

OUTPUT FREQUENCY (MHz) INTEGRATION BANDWIDTH 12 kHz - 5 MHz 1 kHz 5 MHz 12 kHz 20 MHz TYPICAL JITTER (ps, rms) 0.15 0.1

Changes from Original (September 2015) to Revision A Page

Product Preview to Production Data full release................................................................................................................... 1

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NO. POWER n/a DAP Ground Die Attach Pad. The DAP is an electrical connection and provides a thermal dissipation path. For proper electrical and thermal performance of the device, via pattern (0.3 mm holes) is recommended to connect the DAP to multiple ground layers of the PCB. Refer to Layout Guidelines. 3.3 V power supply for digital control and STATUS outputs. 3.3 V power supply for input block. 3.3 V power supply for OUT0/OUT1 channel. 3.3 V power supply for OUT2/OUT3 channel. 3.3 V power supply for PLL LDO. 3.3 V power supply for PLL/VCO. 3.3 V power supply for OUT4 channel. 3.3 V power supply for OUT5 channel. 3.3 V power supply for OUT6 channel. 3.3 V power supply for OUT7 channel. NAME TYPE DESCRIPTION


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