|Title||IC CPLD 32MC 5.5NS 32QFN|
|Datasheet||Download XC2C32A-6QFG32C datasheet
|Others parts numbering|
|XC2C32A-6VQG44C: IC CPLD 32MC 5.5NS 44VQFP|
|XC2C64A-7VQG44C: IC CPLD 64MC 6.7NS 44VQFP|
|XC2C64A-7QFG48C: IC CPLD 64MC 6.7NS 48QFN|
|XC2C64A-7CPG56C: IC CPLD 64MC 6.7NS 56BGA|
|XC2C64A-7VQG44I: IC CPLD 64MC 6.7NS 44VQFP|
|XC2C64A-7QFG48I: IC CPLD 64MC 6.7NS 48QFN|
|XC2C64A-7VQG100C: IC CPLD 64MC 6.7NS 100VQFP|
|XC2C64A-7CPG56I: IC CPLD 64MC 6.7NS 56CSBGA|
|XC2C64A-5VQG44C: IC CPLD 64MC 4.6NS 44VQFP|
|XC2C64A-5QFG48C: IC CPLD 64MC 4.6NS 48QFN|
|XC2C64A-7VQG100I: IC CPLD 64MC 6.7NS 100VQFP|
|XC2C128-7VQG100C: IC CPLD 128MC 7NS 100VQFP|
|410-146: KIT STARTER COOLRUNNER-II|
Optimized for 1.8V systems - As fast 3.8 ns pin-to-pin logic delays - As low 12 A quiescent current Industry's best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation: 1.5V through 3.3V Available in multiple package options - 32-land QFN with 21 user I/Os - 44-pin VQFP with 33 user I/Os 56-ball CP BGA with 33 user I/Os - Pb-free available for all packages Advanced system features - Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Two separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes - Optional DualEDGE triggered registers - Global signal options with macrocell control Multiple global clocks with phase selection per macrocell Multiple global output enables Global set/reset - Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - Advanced design security - Open-drain output option for Wired-OR and LED drive - Optional configurable grounds on unused I/Os - Optional bus-hold, 3-state, or weak pullup on selected I/O pins - Mixed I/O voltages compatible with 1.8V, 2.5V, and 3.3V logic levels - PLA architecture Superior pinout retention 100% product term routability across function block - Hot pluggableDescription
The CoolRunnerTM-II 32-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This device consists of two Function Blocks interconnected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured or T flip-flop a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain, and programmable grounds. A Schmitt trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers can be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset, and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. The CoolRunner-II 32-macrocell CPLD is I/O compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33 (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 32A macrocell device that permit easy interfacing 2.5V, 1.8V, and 1.5V devices.Refer to the CoolRunnerTM-II family data sheet for the architecture description.
© 20042008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Xilinx® CoolRunner-II CPLDs are fabricated a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology. RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high performance and low power operation.
LVCMOS standard is used 3.3V, 2.5V, and 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XC2C32A IOSTANDARD Attribute LVTTL LVCMOS18 LVCMOS15(1)
The CoolRunner-II CPLD 32 macrocell features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. TheNotes: 1. 16-bit up/down, resettable binary counter (one counter per function block).
Symbol VCC VCCIO VJTAG(2) VCCAUX TSTG(3) TJ Description Supply voltage relative to ground Supply voltage for output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative to ground Voltage applied to 3-state output Storage Temperature (ambient) Junction Temperature Value to +150 Units °C
Notes: 1. Maximum DC undershoot below GND must be limited to either or 10 mA, whichever is easiest to achieve. During transitions, the device pins might undershoot 2.0V or overshoot to +4.5V, provided this overshoot or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free packages, see XAPP427.
Symbol VCC VCCIO Parameter Supply voltage for internal logic and input buffers Commercial to +70°C Industrial to +85°C Min Max Units
Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operationDC Electrical Characteristics Over Recommended Operating Conditions
Symbol ICCSB ICC(1) CJTAG CCLK CIO IIL(2) IIH(2) Parameter Standby current Commercial Standby current Industrial Dynamic current JTAG input capacitance Global clock input capacitance I/O capacitance Input leakage current I/O High-Z leakage Test Conditions VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 1 MHz = 50 MHz = 1 MHz = 1 MHz = 1 MHz VIN 0V or VCCIO to 3.9V VIN 0V or VCCIO to 3.9V Typical 22 38 Max. Units pF A
Notes: 1. 16-bit up/down resettable binary counter (one per Function Block) tested at VCC = VCCIO 1.9V. 2. See Quality and Reliability section of the CoolRunner-II family data sheet.
|Some Part number from the same manufacture Xilinx Corp.|
XC18V01 : XC18V00 Series of In-system Programmable Configuration Proms
XC2VP2-5FF1517C : Virtex-ii Pro Field Programmable Gate Array
XC2VP20-5FF1148I : Virtex-ii Pro Field Programmable Gate Array
XC40110XV-09BG560I : XC4000XLA Field Programmable Gate Array
XC4028XLA-8BG256I : XC4000XLA Field Programmable Gate Array
XCS20XL-3PQ208C : Spartan and Spartan-xl Families Field Programmable Gate Arrays
XCS20XL-4CS280C : Spartan and Spartan-xl Families Field Programmable Gate Arrays
XCS40-5TQ84C : Spartan and Spartan-xl Families Field Programmable Gate Arrays
XC5206-3PG156C : Field Programmable Gate Arrays
W1D64M72R8A-5AE-FA : 64M X 8 DDR DRAM MODULE, 0.5 ns, DMA240 Specifications: Memory Category: DRAM Chip ; Density: 536871 kbits ; Number of Words: 64000 k ; Bits per Word: 8 bits ; Package Type: MO-237, DIMM-240 ; Pins: 240 ; Supply Voltage: 1.8V ; Access Time: 0.5000 ns ; Operating Temperature: 0 to 55 C (32 to 131 F)
XC18V01VQG44I : 128K X 8 CONFIGURATION MEMORY, 15 ns, PQFP44 Specifications: Memory Category: PROM ; Density: 1049 kbits ; Number of Words: 128 k ; Bits per Word: 8 bits ; Package Type: PLASTIC, VQFP-44 ; Pins: 44 ; Logic Family: CMOS ; Supply Voltage: 3.3V ; Access Time: 15 ns ; Operating Temperature: -40 to 85 C (-40 to 185 F)
XC2V40-6FG256I : FPGA, 64 CLBS, 40000 GATES, 820 MHz, PBGA144 Specifications: System Gates: 40000 ; Logic Cells / Logic Blocks: 64 ; Package Type: Other, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-216BAG-2, CSP-144 ; Logic Family: CMOS ; Pins: 144 ; Internal Frequency: 820 MHz ; Propagation Delay: 0.3500 ns ; Supply Voltage: 1.5V