Robust Bias Option for 0.15-mm pHEMT MMIC Low-Noise Amplifiers
Category: Telephone, cellular phone and intercom
Manufacture: TriQuint Semiconductor
Datasheet: Download this application note
Product Application Note
Robust Bias Option for 0.15 µm pHEMT MMIC Low-Noise Amplifiers Background: A bias network has been designed for low-noise MMIC amplifiers fabricated using the 0.15 um pHEMT process. This process exhibits a low pinch-off voltage (near zero volts) and the optimum gate-source voltage can be a negative or positive voltage, due to normal process variations.
Method: The circuit shown in Figure 1 below will automatically set the gate voltage (which is equivalently the gate-source voltage because the source is grounded on the MMIC chip) to achieve a desired current target, Id, as defined by Id = (Vpos Vd) / Rd
Vpos Rd Vd RF In Vg R2 Vneg RF Out
Figure 1 This circuit works well with low noise amplifiers for two reasons: 1) The optimum MMIC drain voltage, Vd, is typically 3 to 4 volts so that a voltage dropping resistor (Rd) is already required to reduce the supply voltage from its typical value of 5 to 8 volts. 2) The level of bias current is modest, usually in the range of 50 to 250 mA. This allows easy placement of a small series resistor (Rd) without thermal issues.
Additionally, the circuit is very inexpensive, requiring only one standard, low cost op amp and three resistors. Typically, the MMIC LNA will already have bypass capacitors on the drain and the gate terminals (not shown). The negative voltage applied to the op amp is not critical; it only needs to be more negative than the pinch-off voltage (this depends somewhat on the choice of op amp). Negative 3 to negative 5 volts (-3V to -5V) will satisfy most applications. Also, the op amp provides a low driving impedance at the gate and will sink the small leakage currents that are common in GaAs FETs and pHEMTs without a change in the drain bias current.
Recommended Approach: If the values of Vpos, Vd, Id are known, the next steps will be to: 1) Solve for Rd 2) Solve for resistor ratio 3) Choose R2, solve for R1 Example: The TGA1319A LNA requires a bias quiescent current of 45mA at a drain voltage of 3 volts. The power supply voltage is 5 volts and a negative voltage of -5 volts is available. Knowns: Vpos = 5 volts, Vneg = -5 volts, Vd = 3 volts Rd = (Vpos Vd) / Id, Ratio = R2 / (R1 + R2) = Vd / Vpos, R1 = R2 * (1 ratio) / ratio .
Target: Id = 45 mA Rd = (5 3) / 0.045 = 44.44 ohms Ratio = 3 / 5 = 0.6 Choose R2 = 10 kohms, then R1 = 10 * (1 0.6) / 0.6 = 6.67 kohms The closest 1% standard resistor values for Rd, R1, and R2 are 44.2 ohms, 6.65 kohms and 10.0 kohms which results in a nominal drain current of 45.2 mA instead of 45 mA. Power Dissipated = 1.5 * 0.045 = 67.5 mW
Design Issues: Several other design issues should be considered in development of a bias network for a MMIC LNA. Not all of these issues are relevant for all applications. 1.) Op amp stability The design should ensure that the op amp will be stable driving the load presented by the gate terminal of the MMIC. This includes any bypass capacitors (not shown in Figure 1) which might be attached to this terminal. These capacitors are often necessary to ensure the stability of the MMIC at frequencies much lower than their band of operation. Capacitance values below